📄 mpi_cnfg.h
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#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO{ U8 Flags; /* 00h */ U8 AliasAlpa; /* 01h */ U16 Reserved; /* 02h */ U64 AliasWWNN; /* 04h */ U64 AliasWWPN; /* 0Ch */} fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;typedef struct _CONFIG_PAGE_FC_PORT_5{ fCONFIG_PAGE_HEADER Header; /* 00h */ fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[1]; /* 04h */} fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, FCPortPage5_t, MPI_POINTER pFCPortPage5_t;#define MPI_FCPORTPAGE5_PAGEVERSION (0x00)#define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01)#define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02)typedef struct _CONFIG_PAGE_FC_PORT_6{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved; /* 04h */ U64 TimeSinceReset; /* 08h */ U64 TxFrames; /* 10h */ U64 RxFrames; /* 18h */ U64 TxWords; /* 20h */ U64 RxWords; /* 28h */ U64 LipCount; /* 30h */ U64 NosCount; /* 38h */ U64 ErrorFrames; /* 40h */ U64 DumpedFrames; /* 48h */ U64 LinkFailureCount; /* 50h */ U64 LossOfSyncCount; /* 58h */ U64 LossOfSignalCount; /* 60h */ U64 PrimativeSeqErrCount; /* 68h */ U64 InvalidTxWordCount; /* 70h */ U64 InvalidCrcCount; /* 78h */ U64 FcpInitiatorIoCount; /* 80h */} fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, FCPortPage6_t, MPI_POINTER pFCPortPage6_t;#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_FC_PORT_7{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved; /* 04h */ U8 PortSymbolicName[256]; /* 08h */} fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, FCPortPage7_t, MPI_POINTER pFCPortPage7_t;#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_FC_PORT_8{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 BitVector[8]; /* 04h */} fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, FCPortPage8_t, MPI_POINTER pFCPortPage8_t;#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_FC_PORT_9{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved; /* 04h */ U64 GlobalWWPN; /* 08h */ U64 GlobalWWNN; /* 10h */ U32 UnitType; /* 18h */ U32 PhysicalPortNumber; /* 1Ch */ U32 NumAttachedNodes; /* 20h */ U16 IPVersion; /* 24h */ U16 UDPPortNumber; /* 26h */ U8 IPAddress[16]; /* 28h */ U16 Reserved1; /* 38h */ U16 TopologyDiscoveryFlags; /* 3Ah */} fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, FCPortPage9_t, MPI_POINTER pFCPortPage9_t;#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)/****************************************************************************//* FC Device Config Pages *//****************************************************************************/typedef struct _CONFIG_PAGE_FC_DEVICE_0{ fCONFIG_PAGE_HEADER Header; /* 00h */ U64 WWNN; /* 04h */ U64 WWPN; /* 0Ch */ U32 PortIdentifier; /* 14h */ U8 Protocol; /* 18h */ U8 Flags; /* 19h */ U16 BBCredit; /* 1Ah */ U16 MaxRxFrameSize; /* 1Ch */ U8 Reserved1; /* 1Eh */ U8 PortNumber; /* 1Fh */ U8 FcPhLowestVersion; /* 20h */ U8 FcPhHighestVersion; /* 21h */ U8 CurrentTargetID; /* 22h */ U8 CurrentBus; /* 23h */} fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02)#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)/****************************************************************************//* RAID Volume Config Pages *//****************************************************************************/typedef struct _RAIDVOL2_IM_PHYS_ID{ U8 TargetID; /* 00h */ U8 Bus; /* 01h */ U8 IocNumber; /* 02h */ U8 PhysDiskNumber; /* 03h */ U8 Reserved[8]; /* 04h */ U8 PhysicalDiskIdentifier[16]; /* 0Ch */ U8 VendorId[8]; /* 1Ch */ U8 ProductId[16]; /* 24h */ U8 ProductRevLevel[4]; /* 34h */ U32 Reserved1; /* 38h */ U8 Info[32]; /* 3Ch */} RAIDVOL2_IM_PHYS_ID, MPI_POINTER PTR_RAIDVOL2_IM_PHYS_ID, RaidVol2ImPhysicalID_t, MPI_POINTER pRaidVol2ImPhysicalID_t;typedef struct _RAIDVOL2_IM_DISK_INFO{ U32 DiskStatus; /* 00h */ U32 DeviceSettings; /* 04h */ U16 ErrorCount; /* 08h */ U16 Reserved; /* 0Ah */ U8 ErrorCdbByte; /* 0Ch */ U8 ErrorSenseKey; /* 0Dh */ U8 ErrorASC; /* 0Eh */ U8 ErrorASCQ; /* 0Fh */ U16 SmartCount; /* 10h */ U8 SmartASC; /* 12h */ U8 SmartASCQ; /* 13h */} RAIDVOL2_IM_DISK_INFO, MPI_POINTER PTR_RAIDVOL2_IM_DISK_INFO, RaidVol2ImDiskInfo_t, MPI_POINTER pRaidVol2ImDiskInfo_t;/* RAID Volume 2 IM Physical Disk DiskStatus flags */#define MPI_RVP2_PHYS_DISK_PRIMARY (0x00000001)#define MPI_RVP2_PHYS_DISK_SECONDARY (0x00000002)#define MPI_RVP2_PHYS_DISK_HOT_SPARE (0x00000004)#define MPI_RVP2_PHYS_DISK_OUT_OF_SYNC (0x00000008)#define MPI_RVP2_PHYS_DISK_STATUS_MASK (0x00000F00)#define MPI_RVP2_PHYS_DISK_STATUS_ONLINE (0x00000000)#define MPI_RVP2_PHYS_DISK_STATUS_MISSING (0x00000100)#define MPI_RVP2_PHYS_DISK_STATUS_NOT_COMPATIBLE (0x00000200)#define MPI_RVP2_PHYS_DISK_STATUS_FAILED (0x00000300)#define MPI_RVP2_PHYS_DISK_STATUS_INITIALIZING (0x00000400)#define MPI_RVP2_PHYS_DISK_STATUS_OFFLINE_REQUESTED (0x00000500)#define MPI_RVP2_PHYS_DISK_STATUS_OTHER_OFFLINE (0x00000F00)typedef struct _RAIDVOL2_IM_PHYSICAL_DISK{ RAIDVOL2_IM_PHYS_ID Id; /* 00h */ RAIDVOL2_IM_DISK_INFO Info; /* 5Ch */} RAIDVOL2_IM_PHYSICAL_DISK, MPI_POINTER PTR_RAIDVOL2_IM_PHYSICAL_DISK, RaidVol2ImPhysicalDisk_t, MPI_POINTER pRaidVol2ImPhysicalDisk_t;#define MPI_RAIDVOLPAGE2_MAX_DISKS (3)typedef struct _CONFIG_PAGE_RAID_VOL_2{ fCONFIG_PAGE_HEADER Header; /* 00h */ U32 VolumeStatus; /* 04h */ U32 VolumeSettings; /* 08h */ U32 Reserved; /* 0Ch */ U64 MaxLba; /* 10h */ U32 BlockSize; /* 18h */ U8 Reserved1; /* 1Ch */ U8 NumPhysicalDisks; /* 1Dh */ U16 Reserved2; /* 1Eh */ RAIDVOL2_IM_PHYSICAL_DISK IMPhysicalDisk[MPI_RAIDVOLPAGE2_MAX_DISKS];} fCONFIG_PAGE_RAID_VOL_2, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_2, RaidVolumePage2_t, MPI_POINTER pRaidVolumePage2_t;#define MPI_RAIDVOLPAGE2_PAGEVERSION (0x00)/* RAID Volume Page 2 VolumeStatus defines */#define MPI_RAIDVOLPAGE2_STATUS_ENABLED (0x00000001)#define MPI_RAIDVOLPAGE2_STATUS_QUIESCED (0x00000002)#define MPI_RAIDVOLPAGE2_STATUS_RESYNC_IN_PROGRESS (0x00000004)#define MPI_RAIDVOLPAGE2_STATUS_DEGRADED (0x00000008)/* RAID Volume Page 2 VolumeSettings defines */#define MPI_RAIDVOLPAGE2_SETTING_WRITE_CACHING_ENABLE (0x00000001)#define MPI_RAIDVOLPAGE2_SETTING_OFFLINE_ON_SMART (0x00000002)#define MPI_RAIDVOLPAGE2_SETTING_AUTO_CONFIGURE (0x00000004)#define MPI_RAIDVOLPAGE2_SETTING_USE_DEFAULTS (0x80000000)/****************************************************************************//* LAN Config Pages *//****************************************************************************/typedef struct _CONFIG_PAGE_LAN_0{ ConfigPageHeader_t Header; /* 00h */ U16 TxRxModes; /* 04h */ U16 Reserved; /* 06h */ U32 PacketPrePad; /* 08h */} fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, LANPage0_t, MPI_POINTER pLANPage0_t;#define MPI_LAN_PAGE0_PAGEVERSION (0x01)#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)typedef struct _CONFIG_PAGE_LAN_1{ ConfigPageHeader_t Header; /* 00h */ U16 Reserved; /* 04h */ U8 CurrentDeviceState; /* 06h */ U8 Reserved1; /* 07h */ U32 MinPacketSize; /* 08h */ U32 MaxPacketSize; /* 0Ch */ U32 HardwareAddressLow; /* 10h */ U32 HardwareAddressHigh; /* 14h */ U32 MaxWireSpeedLow; /* 18h */ U32 MaxWireSpeedHigh; /* 1Ch */ U32 BucketsRemaining; /* 20h */ U32 MaxReplySize; /* 24h */ U32 NegWireSpeedHigh; /* 28h */ U32 NegWireSpeedLow; /* 2Ch */} fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, LANPage1_t, MPI_POINTER pLANPage1_t;#define MPI_LAN_PAGE1_PAGEVERSION (0x03)#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)#endif⌨️ 快捷键说明
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