pci_v3.c

内核linux2.4.20,可跟rtlinux3.2打补丁 组成实时linux系统,编译内核

	unsigned long flags;
	u8 v;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	v = __raw_readb(addr);

	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int v3_read_config_word(struct pci_dev *dev, int where, u16 *val)
{
	unsigned long addr;
	unsigned long flags;
	u16 v;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	v = __raw_readw(addr);

	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int v3_read_config_dword(struct pci_dev *dev, int where, u32 *val)
{
	unsigned long addr;
	unsigned long flags;
	u32 v;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	v = __raw_readl(addr);

	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int v3_write_config_byte(struct pci_dev *dev, int where, u8 val)
{
	unsigned long addr;
	unsigned long flags;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	__raw_writeb(val, addr);
	__raw_readb(addr);
	
	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int v3_write_config_word(struct pci_dev *dev, int where, u16 val)
{
	unsigned long addr;
	unsigned long flags;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	__raw_writew(val, addr);
	__raw_readw(addr);

	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int v3_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
	unsigned long addr;
	unsigned long flags;

	spin_lock_irqsave(&v3_lock, flags);
	addr = v3_open_config_window(dev, where);

	__raw_writel(val, addr);
	__raw_readl(addr);

	v3_close_config_window();
	spin_unlock_irqrestore(&v3_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_v3_ops = {
	read_byte:	v3_read_config_byte,
	read_word:	v3_read_config_word,
	read_dword:	v3_read_config_dword,
	write_byte:	v3_write_config_byte,
	write_word:	v3_write_config_word,
	write_dword:	v3_write_config_dword,
};

static struct resource non_mem = {
	name:	"PCI non-prefetchable",
	start:	0x40000000 + PCI_BUS_NONMEM_START,
	end:	0x40000000 + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
	flags:	IORESOURCE_MEM,
};

static struct resource pre_mem = {
	name:	"PCI prefetchable",
	start:	0x40000000 + PCI_BUS_PREMEM_START,
	end:	0x40000000 + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
	flags:	IORESOURCE_MEM | IORESOURCE_PREFETCH,
};

void __init pci_v3_setup_resources(struct resource **resource)
{
	if (request_resource(&iomem_resource, &non_mem))
		printk("PCI: unable to allocate non-prefetchable memory region\n");
	if (request_resource(&iomem_resource, &pre_mem))
		printk("PCI: unable to allocate prefetchable memory region\n");

	/*
	 * bus->resource[0] is the IO resource for this bus
	 * bus->resource[1] is the mem resource for this bus
	 * bus->resource[2] is the prefetch mem resource for this bus
	 */
	resource[0] = &ioport_resource;
	resource[1] = &non_mem;
	resource[2] = &pre_mem;
}

/*
 * These don't seem to be implemented on the Integrator I have, which
 * means I can't get additional information on the reason for the pm2fb
 * problems.  I suppose I'll just have to mind-meld with the machine. ;)
 */
#define SC_PCI     (IO_ADDRESS(INTEGRATOR_SC_PCIENABLE))
#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE+0x20))
#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE+0x24))

static int v3_fault(unsigned long addr, struct pt_regs *regs)
{
	unsigned long pc = instruction_pointer(regs);
	unsigned long instr = *(unsigned long *)pc;

	printk("V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
		addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
		v3_readb(V3_LB_ISTAT));

	v3_writeb(V3_LB_ISTAT, 0);
	__raw_writel(3, SC_PCI);

	/*
	 * If the instruction being executed was a read,
	 * make it look like it read all-ones.
	 */
	if ((instr & 0x0c100000) == 0x04100000) {
		int reg = (instr >> 12) & 15;
		unsigned long val;

		if (instr & 0x00400000)
			val = 255;
		else
			val = -1;

		regs->uregs[reg] = val;
		regs->ARM_pc += 4;
		return 0;
	}

	return 1;
}

static void v3_irq(int irq, void *devid, struct pt_regs *regs)
{
	unsigned long pc = instruction_pointer(regs);
	unsigned long instr = *(unsigned long *)pc;
	char buf[128];

	sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", irq,
		pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
		v3_readb(V3_LB_ISTAT));
	printascii(buf);

	v3_writeb(V3_LB_ISTAT, 0);
	__raw_writel(3, SC_PCI);

	/*
	 * If the instruction being executed was a read,
	 * make it look like it read all-ones.
	 */
	if ((instr & 0x0c100000) == 0x04100000) {
		int reg = (instr >> 16) & 15;
		sprintf(buf, "   reg%d = %08lx\n", reg, regs->uregs[reg]);
		printascii(buf);
	}
}

static struct irqaction v3_int = {
	name: "V3",
	handler: v3_irq,
};
static struct irqaction v3_int2 = {
	name: "V3TM",
	handler: v3_irq,
};

extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);

/*
 * V3_LB_BASE? - local bus address
 * V3_LB_MAP?  - pci bus address
 */
void __init pci_v3_init(void *sysdata)
{
	unsigned int pci_cmd;
	unsigned long flags;

	/*
	 * Hook in our fault handler for PCI errors
	 */
	external_fault = v3_fault;

	spin_lock_irqsave(&v3_lock, flags);

	/*
	 * Setup window 0 - PCI non-prefetchable memory
	 *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
	 */
	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
	v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
			V3_LB_MAP_TYPE_MEM);

	/*
	 * Setup window 1 - PCI prefetchable memory
	 *  Local: 0x50000000 Bus: 0x10000000 Size: 256MB
	 */
	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
			V3_LB_BASE_ENABLE);
	v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
			V3_LB_MAP_TYPE_MEM_MULTIPLE);

	/*
	 * Setup window 2 - PCI IO
	 */
	v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
			V3_LB_BASE_ENABLE);
	v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));

	spin_unlock_irqrestore(&v3_lock, flags);

	pci_scan_bus(0, &pci_v3_ops, sysdata);

	pci_cmd = PCI_COMMAND_MEMORY |
		  PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;

	v3_writew(V3_PCI_CMD, pci_cmd);

	/*
	 * Clear any error conditions.
	 */
	__raw_writel(3, SC_PCI);
	v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
	v3_writeb(V3_LB_ISTAT, 0);
	v3_writeb(V3_LB_IMASK, 0x68);

	printk("LB_CFG: %04x LB_ISTAT: %02x LB_IMASK: %02x\n",
		v3_readw(V3_LB_CFG),
		v3_readb(V3_LB_ISTAT),
		v3_readb(V3_LB_IMASK));
	setup_arm_irq(IRQ_V3INT, &v3_int);
//	setup_arm_irq(IRQ_LBUSTIMEOUT, &v3_int2);
}