📄 init.s
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;**************************************************************************
; *
; PROJECT : ARM9 port test *
; *
; MODULE : INIT.s *
; *
; AUTHOR : samping *
; URL : *
; EMAIL: samping1982@yahoo.com.cn *
; *
; PROCESSOR : EP9302 (32 bit ARM920T RISC core from CIRRUS Logic) *
; *
; IDE : SDT 2.51 & ADS 1.2 *
; *
; DESCRIPTION : *
; EP9302 processor Start up assembly code file. *
; DATE : 2007.3.9 *
; *
;*************************************************************************/
;**************************************************************************
;
;修改人: tsczz
;修改日期: 3.21
;
;**************************************************************************
; Register definition
EP9302_WATCHDOG EQU 0x80940000
VIC1_base EQU 0x800b0000
VIC2_base EQU 0x800c0000
VIC1IntClear EQU (VIC1_base+0x0014)
VIC2IntClear EQU (VIC2_base+0x0014)
EP9302_SDRAMCTRL EQU 0x80060000
EP9302_SDRAMCTRL_GlConfig EQU (EP9302_SDRAMCTRL+0x0004)
EP9302_SDRAMCTRL_RefrshTimr EQU (EP9302_SDRAMCTRL+0x0008)
EP9302_SDRAMCTRL_BootSts EQU (EP9302_SDRAMCTRL+0x000c)
EP9302_SDRAMCTRL_DEVCFG_0 EQU (EP9302_SDRAMCTRL+0x0010)
EP9302_SDRAMCTRL_DEVCFG_1 EQU (EP9302_SDRAMCTRL+0x0014)
EP9302_SDRAMCTRL_DEVCFG_2 EQU (EP9302_SDRAMCTRL+0x0018)
EP9302_SDRAMCTRL_DEVCFG_3 EQU (EP9302_SDRAMCTRL+0x001c)
EP9302_CLKSET1 EQU 0x80930020
R1_I EQU (1<<12)
R1_M EQU (1)
;Pre-defined MODE constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;Pre-defined stack size
_USE_STKSIZE EQU 256
_SVC_STKSIZE EQU 256*9
_UND_STKSIZE EQU 256
_ABT_STKSIZE EQU 256
_IRQ_STKSIZE EQU 256
_FIQ_STKSIZE EQU 0
SRAM_SADDR EQU 0x00000000
SRAM_SIZE EQU 32*1024*1024 ; 32M SDRAM
SRAM_EADDR EQU SRAM_SADDR+SRAM_SIZE-1 ; SRAM end address
STK_SIZE EQU _SVC_STKSIZE+_UND_STKSIZE+_ABT_STKSIZE+_IRQ_STKSIZE+_FIQ_STKSIZE
STK_SADDR EQU SRAM_EADDR+1-STK_SIZE
ISR_BADDR EQU 0x00100000
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=$HandleLabel
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
MEND
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
AREA Start, CODE, READONLY
ENTRY
ResetEntry
b ResetHandler ; for debug
b HandlerUndef ; handlerUndef
b HandlerSWI ; SWI interrupt handler
b HandlerPabort ; handlerPAbort
b HandlerDabort ; handlerDAbort
b . ; handlerReserved
b HandlerIRQ ; handlerIRQ
b HandlerFIQ ; handlerFIQ
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;*****************************************************************************
;
; ResetHandler is the startup code to be used
;
;*****************************************************************************
ResetHandler
ldr r0,=EP9302_WATCHDOG ; watch dog disable
ldr r1,=0xAA55
str r1,[r0]
ldr r0,=VIC1IntClear
ldr r1,=0xffffffff ; VIC1 interrupt disable
str r1,[r0]
ldr r0,=VIC2IntClear ; VIC2 interrupt disable
str r1,[r0]
; **************************************************************************
;pll setting
; **************************************************************************
;pll1
ldr r0,=0x6+(0x7<<5)+(0x17<<11)+(0x1<<16)+(0x0<<18)+(0x2<<20)+(0x1<<23)+(0x1<<24)+(0x0<<25)
ldr r1,=EP9302_CLKSET1
str r0,[r1]
NOP
NOP
NOP
NOP
NOP
;pll2 disable at reset by default
;******************************************************************************
;disable mmu
;******************************************************************************
;void MMU_DisableMMU
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_M
mcr p15,0,r0,c1,c0,0
;void MMU_DisableICache
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_I
mcr p15,0,r0,c1,c0,0
;****************************************************************************
;Define Stacks
;The follow section defines the stack pointer for IRQ and SVC modes.
;This is optional as the debugger will assign its own stack area with the
;$top_of_memory variable in "debugger internals".
;However, this code is necessary if this program is used to launch an
;embedded applications in C or assembly.
;****************************************************************************
ldr sp,=SVCStack ; Why?
bl InitStacks
;*****************************************************************************
; 初始化C程序的运行环境
;*****************************************************************************
LDR R0,=|Image$$RO$$Limit|
LDR R1,=|Image$$RW$$Base|
LDR R3,=|Image$$ZI$$Base|
; 如果映像文件只有一个执行域,那么Image$$RO$$Limit和Image$$RW$$Base
CMP R0,R1 ; 是一样的,也即是execution view下RW section下的地址和load view
BEQ LOOP1 ; 下RW section的地址相同,这样不需要移动RW section
LOOP0 CMP R1,R3 ; 当不相等时,就需要copy RW section 到execution view下指定地址
LDRCC R2,[R0],#4
STRCC R2,[R1],#4
BCC LOOP0
LOOP1 LDR R1,=|Image$$ZI$$Limit| ;为初始化ZI section段做一些准备工作
MOV R2,#0
LOOP2 CMP R3,R1 ;真正初始化ZI section段
STRCC R2,[R3],#4
BCC LOOP2
;*****************************************************************************
; end初始化C程序的运行环境
program
;
; Call the actual C program.
; Should never return.
;
IMPORT Main
B Main
InitStacks
; Do not use DRAM,such as stmfd,ldmfd......
; SVCstack is initialized before
; Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ; UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ; AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ; IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ; FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ; SVCMode
ldr sp,=SVCStack
; USER mode is not initialized.
mov pc,lr ; The LR register may be not valid for the mode changes.
;*****************************************************************************
;
; Zero-initialized read/write data area for stacks.
; This area is determined by the RW value in the Linker under "entry and base".
;*****************************************************************************
AREA SYS_STK, DATA, READWRITE, NOINIT
;*****************************************************************************
;
; Memory buffers to contain the stacks for the various processor modes which
; we will be using.
;
;*****************************************************************************
^ (ISR_BADDR-0xD00)
UserStack # _SVC_STKSIZE
SVCStack # _UND_STKSIZE
UndefStack # _ABT_STKSIZE
AbortStack # _IRQ_STKSIZE
IRQStack # _FIQ_STKSIZE
FIQStack # 0
AREA ISR_HOOK, DATA, READWRITE, NOINIT
^ ISR_BADDR
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
HandleUnused1 # 4
HandleUnused2 # 4
HandleCOMMRX # 4
HandleCOMMTX # 4
HandleTC1OI # 4
HandleTC2OI # 4
HandleAACINTR # 4
HandleDMAM2P0 # 4
HandleDMAM2P1 # 4
HandleDMAM2P2 # 4
HandleDMAM2P3 # 4
HandleDMAM2P4 # 4
HandleDMAM2P5 # 4
HandleDMAM2P6 # 4
HandleDMAM2P7 # 4
HandleDMAM2P8 # 4
HandleDMAM2P9 # 4
HandleDMAM2M0 # 4
HandleDMAM2M1 # 4
HandleReserved3 # 4
HandleGPIO0INTR # 4
HandleGPIO1INTR # 4
HandleGPIO2INTR # 4
HandleUART1RXINTR1 # 4
HandleUART1TXINTR1 # 4
HandleUART2RXINTR2 # 4
HandleUART2TXINTR2 # 4
HandleReserved4 # 4
HandleReserved5 # 4
HandleReserved6 # 4
HandleReserved7 # 4
HandleReserved8 # 4
HandleINT_EXT0 # 4
HandleINT_EXT1 # 4
HandleReserved9 # 4
HandleTINTR # 4
HandleWEINT # 4
HandleINT_RTC # 4
HandleINT_IrDA # 4
HandleINT_MAC # 4
HandleINT_EXT2 # 4
HandleReserved10 # 4
HandleReserved11 # 4
HandleReserved12 # 4
HandleReserved13 # 4
HandleINT_SSP1RX # 4
HandleINT_SSP1TX # 4
HandleReserved14 # 4
HandleReserved15 # 4
HandleReserved16 # 4
HandleReserved17 # 4
HandleTC3OI # 4
HandleINT_UART1 # 4
HandleSSPINTR # 4
HandleINT_UART2 # 4
HandleReserved18 # 4
HandleUSHINTR # 4
HandleReserved19 # 4
HandleReserved20 # 4
HandleGPIOINTR # 4
HandleSAIINTR # 4
HandleUnused21 # 4
HandleUnused22 # 4
HandleUnused23 # 4
;
;*****************************************************************************
;
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