mmumacro.s

GM8120 linux driver.

;/***************************************************************************
;   Copyright ARM Limited 1998 - 2000.  All rights reserved.
;****************************************************************************
;
;   mmumacro.s
;
;	$Id: mmumacro.s,v 1.1.1.1 2002/12/06 05:23:02 bruce Exp $
;
;   Generic aliases for COPROCESSOR access macros for ARM processors.
;
;****************************************************************************/

 IF :LNOT: :DEF: __mmumacros
__mmumacros             EQU     1

; Bit definitions are here
	INCLUDE	mmu_h.s

; Macros for MMU/MPU page tables:
	INCLUDE	paget.s


; Dummy macros for processors without MMU/MPU etc.
	INCLUDE	nommu.s

;-----------------------------------------------------------------------
; NOTE: Most (all?) macros call the NO_* macro first. These macros must
;	be non-destructive on passed parameters, as one (or more) of
;	the processor-specific macros may be called next.
;	Define HAL_HAS_BLAH for specific processor features to avoid
;	adding NO_BLAH code to the appropriate macros. If not supported,
;	don't define. It doesn't add much code if a feature is
;	supported & not defined (the NO_BLAH macro may be empty).
;HAL_HAS_CP15 HAL_HAS_MMU HAL_HAS_CACHE HAL_HAS_WBUFFER
;HAL_HAS_MPU HAL_HAS_B_PREDICT


 IF :DEF: ARM7T
	INCLUDE	mmu7T.s
 ENDIF

 IF :DEF: ARM720T
	INCLUDE	mmu720T.s
 ENDIF

 IF :DEF: ARM740T
	INCLUDE	mmu740T.s
 ENDIF

 IF :DEF: ARM922
	INCLUDE	mmu920T.s
 ENDIF

 IF :DEF: ARM940T
	INCLUDE	mmu940T.s
 ENDIF

 IF :DEF: ARM946T
	INCLUDE	mmu946T.s
 ENDIF

 IF :DEF: ARM966T
	INCLUDE	mmu966T.s
 ENDIF

 IF :DEF: ARM1020T
	INCLUDE	mmu1020T.s
 ENDIF

 IF :DEF: SA110
	INCLUDE	mmu110.s
 ENDIF

 IF :DEF: XSCALE
	INCLUDE	mmu_xscale.s
 ENDIF

;------------------------------------------------------------------
;	Compulsory Macros:
;
; These are the macros which must be defined, even for processors
; without any memory management capabilities.
;
; CHECK_FOR_MMU	- return TRUE if CPU has an MMU
; CHECK_FOR_MPU	- return TRUE if CPU has an MPU
; CHECK_CACHE	- return TRUE if CPU has a Cache
; CHECK_UNIFIED	- return TRUE if CPU has a Unified Cache
; CHECK_CPUID	- return TRUE if CPU matches the expected ID
; CHECK_VENDOR	- return TRUE if CPU matches the expected Vendor ID
; CHECK_FOR_BRANCH_PRED - return TRUE if CPU implements branch prediction

	MACRO
	CHECK_FOR_MMU	$reg
 IF :LNOT: :DEF: HAL_HAS_MMU
	NO_CHECK_FOR_MMU	$reg
 ENDIF
 IF :DEF: ARM7T
	CHECK_FOR_MMU_7T	$reg
 ENDIF
 IF :DEF: ARM720T
	CHECK_FOR_MMU_720T	$reg
 ENDIF
 IF :DEF: ARM740T
	CHECK_FOR_MMU_740T	$reg
 ENDIF
 IF :DEF: ARM922
	CHECK_FOR_MMU_920T	$reg
 ENDIF
 IF :DEF: ARM940T
	CHECK_FOR_MMU_940T	$reg
 ENDIF
 IF :DEF: ARM946T
	CHECK_FOR_MMU_946T	$reg
 ENDIF
 IF :DEF: ARM1020T
	CHECK_FOR_MMU_1020T	$reg
 ENDIF
 IF :DEF: SA110
	CHECK_FOR_MMU_110	$reg
 ENDIF
 IF :DEF: XSCALE
	CHECK_FOR_MMU_XSCALE	$reg
 ENDIF
	MEND

;Macro to signal if this processor has an MPU
;
	MACRO
	CHECK_FOR_MPU	$reg
 IF :LNOT: :DEF: HAL_HAS_MPU
	NO_CHECK_FOR_MPU	$reg
 ENDIF
 IF :DEF: ARM7T
	CHECK_FOR_MPU_7T	$reg
 ENDIF
 IF :DEF: ARM720T
	CHECK_FOR_MPU_720T	$reg
 ENDIF
 IF :DEF: ARM740T
	CHECK_FOR_MPU_740T	$reg
 ENDIF
 IF :DEF: ARM922
	CHECK_FOR_MPU_920T	$reg
 ENDIF
 IF :DEF: ARM940T
	CHECK_FOR_MPU_940T	$reg
 ENDIF
 IF :DEF: ARM946T
	CHECK_FOR_MPU_946T	$reg
 ENDIF
 IF :DEF: ARM1020T
	CHECK_FOR_MPU_1020T	$reg
 ENDIF
	MEND

;Macro to signal if this processor has a Cache
;
	MACRO
	CHECK_CACHE	$reg
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_CHECK_CACHE	$reg
 ENDIF
 IF :DEF: ARM720T
	CHECK_CACHE_720T	$reg
 ENDIF
 IF :DEF: ARM740T
	CHECK_CACHE_740T	$reg
 ENDIF
 IF :DEF: ARM922
	CHECK_CACHE_920T	$reg
 ENDIF
 IF :DEF: ARM940T
	CHECK_CACHE_940T	$reg
 ENDIF
 IF :DEF: ARM946T
	CHECK_CACHE_946T	$reg
 ENDIF
 IF :DEF: ARM1020T
	CHECK_CACHE_1020T	$reg
 ENDIF
 IF :DEF: SA110
	CHECK_CACHE_110	$reg
 ENDIF
 IF :DEF: XSCALE
	CHECK_CACHE_XSCALE	$reg
 ENDIF
	MEND

;Macro to signal if this processor has a unified cache
;
	MACRO
	CHECK_UNIFIED	$reg
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_CHECK_UNIFIED	$reg
 ENDIF
 IF :DEF: ARM720T
	CHECK_UNIFIED_720T	$reg
 ENDIF
 IF :DEF: ARM740T
	CHECK_UNIFIED_740T	$reg
 ENDIF
 IF :DEF: ARM922
	CHECK_UNIFIED_920T	$reg
 ENDIF
 IF :DEF: ARM940T
	CHECK_UNIFIED_940T	$reg
 ENDIF
 IF :DEF: ARM946T
	CHECK_UNIFIED_946T	$reg
 ENDIF
 IF :DEF: ARM1020T
	CHECK_UNIFIED_1020T	$reg
 ENDIF
 IF :DEF: SA110
	CHECK_UNIFIED_110	$reg
 ENDIF
 IF :DEF: XSCALE
	CHECK_UNIFIED_XSCALE	$reg
 ENDIF
	MEND

	MACRO
	CHECK_CPUID	$reg, $ret
 IF :LNOT: :DEF: HAL_HAS_CP15
	NO_CHECK_CPUID	$reg, $ret
 ENDIF
 IF :DEF: ARM720T
	CHECK_CPUID_720T	$reg, $ret
 ENDIF
 IF :DEF: ARM740T
	CHECK_CPUID_740T	$reg, $ret
 ENDIF
 IF :DEF: ARM922
	CHECK_CPUID_920T	$reg, $ret
 ENDIF
 IF :DEF: ARM940T
	CHECK_CPUID_940T	$reg, $ret
 ENDIF
 IF :DEF: ARM946T
	CHECK_CPUID_946T	$reg, $ret
 ENDIF
 IF :DEF: ARM966T
	CHECK_CPUID_966T	$reg, $ret
 ENDIF
 IF :DEF: ARM1020T
	CHECK_CPUID_1020T	$reg, $ret
 ENDIF
 IF :DEF: SA110
	CHECK_CPUID_110	$reg, $ret
 ENDIF
 IF :DEF: XSCALE
	CHECK_CPUID_XSCALE	$reg, $ret
 ENDIF
	MEND

	MACRO
	CHECK_VENDOR	$reg, $ret
 IF :LNOT: :DEF: HAL_HAS_CP15
	NO_CHECK_VENDOR	$reg, $ret
 ENDIF
 IF :DEF: ARM720T
	CHECK_VENDOR_720T	$reg, $ret
 ENDIF
 IF :DEF: ARM740T
	CHECK_VENDOR_740T	$reg, $ret
 ENDIF
 IF :DEF: ARM922
	CHECK_VENDOR_920T	$reg, $ret
 ENDIF
 IF :DEF: ARM940T
	CHECK_VENDOR_940T	$reg, $ret
 ENDIF
 IF :DEF: ARM946T
	CHECK_VENDOR_946T	$reg, $ret
 ENDIF
 IF :DEF: ARM966T
	CHECK_VENDOR_966T	$reg, $ret
 ENDIF
 IF :DEF: ARM1020T
	CHECK_VENDOR_1020T	$reg, $ret
 ENDIF
 IF :DEF: SA110
	CHECK_VENDOR_110	$reg, $ret
 ENDIF
 IF :DEF: XSCALE
	CHECK_VENDOR_XSCALE	$reg, $ret
 ENDIF
	MEND

	MACRO
	CHECK_FOR_BRANCH_PRED	$reg
 IF :LNOT: :DEF: HAL_HAS_B_PREDICT
	NO_CHECK_FOR_BRANCH_PRED	$reg
 ENDIF
 IF :DEF: ARM1020T
	CHECK_FOR_BRANCH_PRED_1020T	$reg
 ENDIF
	MEND

;------------------------------------------------------------------
; Macros to hide internals of each processors cache implementation
;

	MACRO
	CPWAIT	$dummy		; Wait for CoProcessor action to complete
 IF :DEF: XSCALE
	CPWAIT_XSCALE	$dummy
 ELSE
 	NOP
	NOP
	NOP
 ENDIF
	MEND


; Never set coprocessor bits directly, use the macros. To use:
;	RDMMU_STATE	$reg	; read the flags
;	CLEAR_IDC	$reg	; disable I & D caches
;	SET_MMU		$reg	; enable MMU
;	WRMMU_STATE	$reg	; update the coprocessor
;
; CLEAR_IDC	Clear Instruction & Data Cache Bits (& Write Buffer)
; CLEAR_ICACHE	Clear (at least) Instruction Cache Bits
; CLEAR_DCACHE	Clear (at least) Data Cache Bits
; CLEAR_WBUFFER	Clear Write Buffer Bits
; CLEAR_MMU	Clear MMU Enable Bits
; CLEAR_BIGEND	Clear Big Endian Enable Bits
; CLEAR_IMEM	Clear On Chip Instruction Memory Enable Bit
; CLEAR_DMEM	Clear On Chip Data Memory Enable Bit	
; SET_IDC	As above, but Set each mode
; SET_ICACHE
; SET_DCACHE
; SET_WBUFFER
; SET_MMU
; SET_BIGEND
; SET_IMEM
; SET_DMEM
; TEST_MMU	Simple tests to see if bits are already set
; TEST_BIGEND

	MACRO
	CLEAR_IDC	$state		; Disable Cache
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_CLEAR_IDC	$state
 ENDIF
 IF :DEF: ARM720T
	CLEAR_IDC_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_IDC_740T	$state
 ENDIF
 IF :DEF: ARM922
	CLEAR_IDC_920T	$state
 ENDIF
 IF :DEF: ARM940T
	CLEAR_IDC_940T	$state
 ENDIF
 IF :DEF: ARM946T
	CLEAR_IDC_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_IDC_1020T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_IDC_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_IDC_XSCALE	$state
 ENDIF
	MEND

	MACRO
	CLEAR_ICACHE	$state		; Disable Instruction Cache
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_CLEAR_ICACHE	$state
 ENDIF
 IF :DEF: ARM720T
	CLEAR_ICACHE_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_ICACHE_740T	$state
 ENDIF
 IF :DEF: ARM922
	CLEAR_ICACHE_920T	$state
 ENDIF
 IF :DEF: ARM940T
	CLEAR_ICACHE_940T	$state
 ENDIF
 IF :DEF: ARM946T
	CLEAR_ICACHE_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_ICACHE_1020T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_ICACHE_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_ICACHE_XSCALE	$state
 ENDIF
	MEND

	MACRO
	CLEAR_DCACHE	$state		; Disable Data Cache
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_CLEAR_DCACHE	$state
 ENDIF
 IF :DEF: ARM720T
	CLEAR_DCACHE_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_DCACHE_740T	$state
 ENDIF
 IF :DEF: ARM922
	CLEAR_DCACHE_920T	$state
 ENDIF
 IF :DEF: ARM940T
	CLEAR_DCACHE_940T	$state
 ENDIF
 IF :DEF: ARM946T
	CLEAR_DCACHE_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_DCACHE_1020T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_DCACHE_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_DCACHE_XSCALE	$state
 ENDIF
	MEND


	MACRO
	CLEAR_PREDICT	$state
 IF :LNOT: :DEF: HAL_HAS_B_PREDICT
	NO_CLEAR_PREDICT	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_PREDICT_1020T	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_PREDICT_XSCALE	$state
 ENDIF
	MEND


	MACRO
	CLEAR_WBUFFER	$state		; Disable Write Buffer
 IF :LNOT: :DEF: HAL_HAS_WBUFFER
	NO_CLEAR_WBUFFER	$state
 ENDIF
 IF :DEF: ARM720T
	CLEAR_WBUFFER_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_WBUFFER_740T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_WBUFFER_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_WBUFFER_XSCALE	$state
 ENDIF
	MEND

	MACRO
	CLEAR_MMU	$state		; Disable MMU
 IF :LNOT: :DEF: HAL_HAS_MMU
	NO_CLEAR_MMU	$state
 ENDIF
 IF :DEF: ARM720T
	CLEAR_MMU_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_MMU_740T	$state
 ENDIF
 IF :DEF: ARM922
	CLEAR_MMU_920T	$state
 ENDIF
 IF :DEF: ARM940T
	CLEAR_MMU_940T	$state
 ENDIF
 IF :DEF: ARM946T
	CLEAR_MMU_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_MMU_1020T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_MMU_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_MMU_XSCALE	$state
 ENDIF
	MEND


	MACRO
	CLEAR_BIGEND	$state		; Disable Big-Endian Mode
	NO_CLEAR_BIGEND	$state
 IF :DEF: ARM720T
	CLEAR_BIGEND_720T	$state
 ENDIF
 IF :DEF: ARM740T
	CLEAR_BIGEND_740T	$state
 ENDIF
 IF :DEF: ARM922
	CLEAR_BIGEND_920T	$state
 ENDIF
 IF :DEF: ARM940T
	CLEAR_BIGEND_940T	$state
 ENDIF
 IF :DEF: ARM946T
	CLEAR_BIGEND_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	CLEAR_BIGEND_1020T	$state
 ENDIF
 IF :DEF: SA110
	CLEAR_BIGEND_110	$state
 ENDIF
 IF :DEF: XSCALE
	CLEAR_BIGEND_XSCALE	$state
 ENDIF
	MEND

	MACRO
	CLEAR_IMEM	$state
 IF :DEF: ARM966T
	CLEAR_IMEM_966T	$state
 ENDIF
	MEND

	MACRO
	CLEAR_DMEM	$state
 IF :DEF: ARM966T
	CLEAR_DMEM_966T	$state
 ENDIF
	MEND

	MACRO
	SET_IDC	$state
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_SET_IDC	$state
 ENDIF
 IF :DEF: ARM720T
	SET_IDC_720T	$state
 ENDIF
 IF :DEF: ARM740T
	SET_IDC_740T	$state
 ENDIF
 IF :DEF: ARM922
	SET_IDC_920T	$state
 ENDIF
 IF :DEF: ARM940T
	SET_IDC_940T	$state
 ENDIF
 IF :DEF: ARM946T
	SET_IDC_946T	$state
 ENDIF
 IF :DEF: ARM1020T
	SET_IDC_1020T	$state
 ENDIF
 IF :DEF: SA110
	SET_IDC_110	$state
 ENDIF
 IF :DEF: XSCALE
	SET_IDC_XSCALE	$state
 ENDIF
	MEND

	MACRO
	SET_ICACHE	$state
 IF :LNOT: :DEF: HAL_HAS_CACHE
	NO_SET_ICACHE	$state
 ENDIF
 IF :DEF: ARM720T
	SET_ICACHE_720T	$state
 ENDIF
 IF :DEF: ARM740T
	SET_ICACHE_740T	$state
 ENDIF
 IF :DEF: ARM922
	SET_ICACHE_920T	$state
 ENDIF
 IF :DEF: ARM940T