powerpc.cpp

ppc750 system design simulator using system c

/***************************************************************************
                          PowerPC.cpp  -  description
                             -------------------
    begin                : Thu Apr 19 2001
    copyright            : (C) 2001 Universite Paris Sud and CEA
    author               : Gilles Mouchard
    email                : [e-mail], gilles.mouchard@.cea.fr
 ***************************************************************************/

#include <stdlib.h>
#include <systemc.h>
#include <PowerPC.h>
#include <time.h>
#include <math.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <ppcemul.h>
#include <signal.h>

PowerPC *PowerPC::powerpc = 0;

PowerPC::PowerPC(const sc_module_name& name)
{
	PowerPC::powerpc = this;
	Build();
	Reset();
}

void PowerPC::Build()
{
	int i;
	
	registersBinding = new RegistersBinding();
	reorderBuffer = new ReorderBuffer();
	

	icache = new ICache("ICache");
	fetchUnit = new FetchUnit("FetchUnit");
	dispatchUnit = new DispatchUnit("DispatchUnit", reorderBuffer, registersBinding);
	
	for(i = 0; i < nIntegerUnit; i++)
	{
		char name[256];
		
		sprintf(name, "IntegerUnit%d", i);
		integerUnit[i] = new IntegerUnit(name);
		integerUnit[i]->inClock(inClock);
	}
	
	for(i = 0; i < nFloatingPointUnits; i++)
	{
		char name[256];
		sprintf(name, "FloatingPointUnit%d", i);
		floatingPointUnit[i] = new FloatingPointUnit(name);
		floatingPointUnit[i]->inClock(inClock);
	}
	
	loadStoreUnit = new LoadStoreUnit("LoadStoreUnit");
	completionUnit = new CompletionUnit("CompletionUnit", reorderBuffer, registersBinding);
	registerFile = new RegisterFile("RegisterFile");
	dcache = new DCache("DCache");
	busInterfaceUnit = new BusInterfaceUnit("BusInterfaceUnit");
	bpu = new BranchPredictionUnit("BranchPredictionUnit");
	branchUnit = new BranchUnit("BranchUnit");
	conditionRegister = new ConditionRegister("ConditionRegister");
	linkRegister = new LinkRegister("LinkRegister");
	countRegister = new CountRegister("CountRegister");
	xerRegister = new XERRegister("XERRegister");
	systemRegisterUnit = new SystemRegisterUnit("SystemRegisterUnit");
	
	icache->inClock(inClock);
	fetchUnit->inClock(inClock);
	dispatchUnit->inClock(inClock);
	loadStoreUnit->inClock(inClock);
	completionUnit->inClock(inClock);
	registerFile->inClock(inClock);
	dcache->inClock(inClock);
	busInterfaceUnit->inClock(inClock);
	bpu->inClock(inClock);
	branchUnit->inClock(inClock);
	conditionRegister->inClock(inClock);
	linkRegister->inClock(inClock);
	countRegister->inClock(inClock);
	xerRegister->inClock(inClock);
	systemRegisterUnit->inClock(inClock);

	fetchUnit->outICacheCancel(icacheCancel);
	fetchUnit->outICacheReq(fetch2icacheReq);
	fetchUnit->outICacheAddr(fetch2icacheAddr);
	fetchUnit->outICacheSize(fetch2icacheSize);
	icache->inCancel(icacheCancel);
	icache->inReq(fetch2icacheReq);
	icache->inAddr(fetch2icacheAddr);
	icache->inSize(fetch2icacheSize);
	icache->outAck(icache2fetchAck);
	icache->outData(icache2fetchReadData);
	icache->outHit(icache2fetchHit);
	fetchUnit->inICacheAck(icache2fetchAck);
	fetchUnit->inICacheData(icache2fetchReadData);
	fetchUnit->inICacheHit(icache2fetchHit);
	
	icache->outMemReq(icache2biuReq);
	icache->outMemAddr(icache2biuAddr);
	busInterfaceUnit->inICacheReq(icache2biuReq);
	busInterfaceUnit->inICacheAddr(icache2biuAddr);
	busInterfaceUnit->outICacheData(biu2icacheReadData);
	busInterfaceUnit->outICacheAck(biu2icacheAck);
	icache->inMemData(biu2icacheReadData);
	icache->inMemAck(biu2icacheAck);
	
	fetchUnit->outReadBHTPC(readBHTPC);
	fetchUnit->outReadBTICPC(readBTICPC);
	bpu->inReadBHTPC(readBHTPC);
	bpu->inReadBTICPC(readBTICPC);
	
	bpu->outReadBHTTakenBranch(readBHTTakenBranch);
	fetchUnit->inReadBHTTakenBranch(readBHTTakenBranch);
	
	bpu->outReadBTICHit(readBTICHit);
	bpu->outReadBTICInstructionsCount(readBTICInstructionsCount);
	
	for(i = 0; i < nInstructionsPerBTICEntry; i++)
	{
		bpu->outReadBTICInstructions[i](readBTICInstructions[i]);
		fetchUnit->inReadBTICInstructions[i](readBTICInstructions[i]);
	}
	
	fetchUnit->inReadBTICHit(readBTICHit);
	fetchUnit->inReadBTICInstructionsCount(readBTICInstructionsCount);
	
	fetchUnit->outUpdateBTIC(updateBTIC);
	fetchUnit->outUpdateBTICPC(updateBTICPC);
	fetchUnit->outUpdateBTICInstructionsCount(updateBTICInstructionsCount);
	
	bpu->inUpdateBTIC(updateBTIC);
	bpu->inUpdateBTICPC(updateBTICPC);
	bpu->inUpdateBTICInstructionsCount(updateBTICInstructionsCount);
	for(i = 0; i < nInstructionsPerBTICEntry; i++)
	{
		fetchUnit->outUpdateBTICInstructions[i](updateBTICInstructions[i]);
		bpu->inUpdateBTICInstructions[i](updateBTICInstructions[i]);
	}

	for(i = 0; i < nIQ; i++)
	{
		fetchUnit->outIQ[i](instructions[i]);
		dispatchUnit->inIQ[i](instructions[i]);
	}
	for(i = 0; i < nBranchQueueEntries; i++)
	{
		fetchUnit->outBranchQueue[i](branchs[i]);
		dispatchUnit->inBranchQueue[i](branchs[i]);
	}
	
	fetchUnit->outInstructionsInQueue(instructionsInQueue);
	dispatchUnit->inInstructionsInQueue(instructionsInQueue);
	fetchUnit->outBranchsInQueue(branchsInQueue);
	dispatchUnit->inBranchsInQueue(branchsInQueue);
	dispatchUnit->outDispatchedInstructions(dispatchedInstructions);
	dispatchUnit->outDispatchedBranchs(dispatchedBranchs);
	fetchUnit->inDispatchedInstructions(dispatchedInstructions);
	fetchUnit->inDispatchedBranchs(dispatchedBranchs);
	
	/* One register file read port is reserved for the system register unit */
	for(i = 0; i < nReadRegisterPorts - 1; i++)
	{
		dispatchUnit->outReadRegisterNumber[i](readRegisterNumber[i]);
		registerFile->inReadRegisterNumber[i](readRegisterNumber[i]);
		registerFile->outReadRegisterData[i](readRegisterData[i]);
		dispatchUnit->inReadRegisterData[i](readRegisterData[i]);
	}
	
	for(i = 0; i < nReadFloatingPointRegisterPorts; i++)
	{
		dispatchUnit->outReadFloatingPointRegisterNumber[i](readFloatingPointRegisterNumber[i]);
		registerFile->inReadFloatingPointRegisterNumber[i](readFloatingPointRegisterNumber[i]);
		registerFile->outReadFloatingPointRegisterData[i](readFloatingPointRegisterData[i]);
		dispatchUnit->inReadFloatingPointRegisterData[i](readFloatingPointRegisterData[i]);
	}
	
	systemRegisterUnit->outReadRegisterNumber(readRegisterNumber[nReadRegisterPorts - 1]);
	registerFile->inReadRegisterNumber[nReadRegisterPorts - 1](readRegisterNumber[nReadRegisterPorts - 1]);
	registerFile->outReadRegisterData[nReadRegisterPorts - 1](readRegisterData[nReadRegisterPorts - 1]);
	systemRegisterUnit->inReadRegisterData(readRegisterData[nReadRegisterPorts - 1]);
	
	for(i = 0; i < nReadRenamePorts; i++)
	{
		dispatchUnit->outReadRenameNumber[i](readRenameNumber[i]);
		registerFile->inReadRenameNumber[i](readRenameNumber[i]);
		registerFile->outReadRenameData[i](readRenameData[i]);
		dispatchUnit->inReadRenameData[i](readRenameData[i]);
	}
	
	for(i = 0; i < nReadFloatingPointRenamePorts; i++)
	{
		dispatchUnit->outReadFloatingPointRenameNumber[i](readFloatingPointRenameNumber[i]);
		registerFile->inReadFloatingPointRenameNumber[i](readFloatingPointRenameNumber[i]);
		registerFile->outReadFloatingPointRenameData[i](readFloatingPointRenameData[i]);
		dispatchUnit->inReadFloatingPointRenameData[i](readFloatingPointRenameData[i]);
	}
	
	for(i = 0; i < nReadRenameCRPorts; i++)
	{
		dispatchUnit->outReadRenameCRNumber[i](readRenameCRNumber[i]);
		conditionRegister->inReadRenameCRNumber[i](readRenameCRNumber[i]);
		conditionRegister->outReadRenameCRData[i](readRenameCRData[i]);
		dispatchUnit->inReadRenameCRData[i](readRenameCRData[i]);
	}
	
	for(i = 0; i < nReadRenameLRPorts; i++)
	{
		dispatchUnit->outReadRenameLRNumber[i](readRenameLRNumber[i]);
		linkRegister->inReadRenameLRNumber[i](readRenameLRNumber[i]);
		linkRegister->outReadRenameLRData[i](readRenameLRData[i]);
		dispatchUnit->inReadRenameLRData[i](readRenameLRData[i]);
	}
	
	for(i = 0; i < nReadRenameCTRPorts; i++)
	{
		dispatchUnit->outReadRenameCTRNumber[i](readRenameCTRNumber[i]);
		countRegister->inReadRenameCTRNumber[i](readRenameCTRNumber[i]);
		countRegister->outReadRenameCTRData[i](readRenameCTRData[i]);
		dispatchUnit->inReadRenameCTRData[i](readRenameCTRData[i]);
	}	
	
	/* Integer unit  */
	for(i = 0; i < nIntegerUnit; i++)
	{
		integerUnit[i]->outBusy(integerBusy[i]);
		dispatchUnit->inIntegerBusy[i](integerBusy[i]);
		dispatchUnit->outIntegerDispatched[i](integerDispatched[i]);
		dispatchUnit->outIntegerOperation[i](integerOperation[i]);
		dispatchUnit->outIntegerOperands[i](integerOperands[i]);
		dispatchUnit->outIntegerTags[i](integerTags[i]);
		dispatchUnit->outIntegerBranchCounter[i](integerBranchCounter[i]);
		completionUnit->outIntegerExecute[i](integerExecute[i]);
		completionUnit->outIntegerExecuteTag[i](integerExecuteTag[i]);
		dispatchUnit->inIntegerExecute[i](integerExecute[i]);
		dispatchUnit->inIntegerExecuteTag[i](integerExecuteTag[i]);
		integerUnit[i]->inDispatched(integerDispatched[i]);
		integerUnit[i]->inOperation(integerOperation[i]);
		integerUnit[i]->inOperands(integerOperands[i]);
		integerUnit[i]->inTags(integerTags[i]);
		integerUnit[i]->inCarry(carry);
		integerUnit[i]->inBranchFinished(branchFinished);
		integerUnit[i]->inMispredictedBranch(mispredictedBranch);
		integerUnit[i]->inBranchCounter(integerBranchCounter[i]);
#if defined(DEBUG) || defined(TRACE)
		dispatchUnit->outIntegerInstructionCounter[i](integerInstructionCounter[i]);
		dispatchUnit->outIntegerProgramCounter[i](integerProgramCounter[i]);
		dispatchUnit->outIntegerInstruction[i](integerInstruction[i]);
		integerUnit[i]->inInstructionCounter(integerInstructionCounter[i]);
		integerUnit[i]->inProgramCounter(integerProgramCounter[i]);
		integerUnit[i]->inInstruction(integerInstruction[i]);
#endif
	}
		
	/* Floating point unit */
	for(i = 0; i < nFloatingPointUnits; i++)
	{
		floatingPointUnit[i]->outBusy(floatingPointBusy[i]);
		floatingPointUnit[i]->outFloatingPointPipelineEmpty(floatingPointPipelineEmpty[i]);
		dispatchUnit->inFloatingPointBusy[i](floatingPointBusy[i]);
		dispatchUnit->inFloatingPointPipelineEmpty[i](floatingPointPipelineEmpty[i]);
		dispatchUnit->outFloatingPointDispatched[i](floatingPointDispatched[i]);
		dispatchUnit->outFloatingPointOperation[i](floatingPointOperation[i]);
		dispatchUnit->outFloatingPointOperands[i](floatingPointOperands[i]);
		dispatchUnit->outFloatingPointTags[i](floatingPointTags[i]);
		dispatchUnit->outFloatingPointBranchCounter[i](floatingPointBranchCounter[i]);
		completionUnit->outFloatingPointExecute[i](floatingPointExecute[i]);
		completionUnit->outFloatingPointExecuteTag[i](floatingPointExecuteTag[i]);
		dispatchUnit->inFloatingPointExecute[i](floatingPointExecute[i]);
		dispatchUnit->inFloatingPointExecuteTag[i](floatingPointExecuteTag[i]);
		floatingPointUnit[i]->inDispatched(floatingPointDispatched[i]);
		floatingPointUnit[i]->inOperation(floatingPointOperation[i]);
		floatingPointUnit[i]->inOperands(floatingPointOperands[i]);
		floatingPointUnit[i]->inTags(floatingPointTags[i]);
		floatingPointUnit[i]->inBranchFinished(branchFinished);
		floatingPointUnit[i]->inMispredictedBranch(mispredictedBranch);
		floatingPointUnit[i]->inBranchCounter(floatingPointBranchCounter[i]);
#if defined(DEBUG) || defined(TRACE)
		dispatchUnit->outFloatingPointInstructionCounter[i](floatingPointInstructionCounter[i]);
		dispatchUnit->outFloatingPointProgramCounter[i](floatingPointProgramCounter[i]);
		dispatchUnit->outFloatingPointInstruction[i](floatingPointInstruction[i]);
		floatingPointUnit[i]->inInstructionCounter(floatingPointInstructionCounter[i]);
		floatingPointUnit[i]->inProgramCounter(floatingPointProgramCounter[i]);
		floatingPointUnit[i]->inInstruction(floatingPointInstruction[i]);
#endif
	}
	
	/* load/store unit */
	loadStoreUnit->outBusy(loadStoreBusy);
	dispatchUnit->inLoadStoreBusy(loadStoreBusy);
	dispatchUnit->outLoadStoreDispatched(loadStoreDispatched);
	dispatchUnit->outLoadStoreOperation(loadStoreOperation);
	dispatchUnit->outLoadStoreOperands(loadStoreOperands);
	dispatchUnit->outLoadStoreTags(loadStoreTags);
	dispatchUnit->outLoadStoreBranchCounter(loadStoreBranchCounter);
	loadStoreUnit->inDispatched(loadStoreDispatched);
	loadStoreUnit->inOperation(loadStoreOperation);
	loadStoreUnit->inOperands(loadStoreOperands);
	loadStoreUnit->inTags(loadStoreTags);
	loadStoreUnit->inBranchCounter(loadStoreBranchCounter);
	loadStoreUnit->inBranchFinished(branchFinished);
	loadStoreUnit->inMispredictedBranch(mispredictedBranch);
	
	loadStoreUnit->outStoreQueueStalled(storeQueueStalled);
	dispatchUnit->inStoreQueueStalled(storeQueueStalled);
	loadStoreUnit->outLoadQueueStalled(loadQueueStalled);
	dispatchUnit->inLoadQueueStalled(loadQueueStalled);
	loadStoreUnit->outEmpty(loadStoreEmpty);
	dispatchUnit->inLoadStoreEmpty(loadStoreEmpty);
	
#if defined(DEBUG) || defined(TRACE)
	dispatchUnit->outLoadStoreInstructionCounter(loadStoreInstructionCounter);
	dispatchUnit->outLoadStoreProgramCounter(loadStoreProgramCounter);
	dispatchUnit->outLoadStoreInstruction(loadStoreInstruction);
	loadStoreUnit->inInstructionCounter(loadStoreInstructionCounter);
	loadStoreUnit->inProgramCounter(loadStoreProgramCounter);
	loadStoreUnit->inInstruction(loadStoreInstruction);
#endif
	/* branch unit */
	dispatchUnit->outBranchDispatched(branchDispatched);
	dispatchUnit->outBranchOperation(branchOperation);
	dispatchUnit->outBranchOperands(branchOperands);
	dispatchUnit->outBranchTags(branchTags);
	branchUnit->inDispatched(branchDispatched);
	branchUnit->inOperation(branchOperation);
	branchUnit->inOperands(branchOperands);
	branchUnit->inTags(branchTags);
	
	branchUnit->outBusy(branchBusy);
	dispatchUnit->inBranchBusy(branchBusy);
	
#if defined(DEBUG) || defined(TRACE)
	dispatchUnit->outBranchInstructionCounter(branchInstructionCounter);
	dispatchUnit->outBranchInstruction(branchInstruction);
	branchUnit->inInstructionCounter(branchInstructionCounter);
	branchUnit->inInstruction(branchInstruction);
#endif
	/* system register unit */
	dispatchUnit->outSystemRegisterDispatched(systemRegisterDispatched);
	dispatchUnit->outSystemRegisterOperation(systemRegisterOperation);
	dispatchUnit->outSystemRegisterTags(systemRegisterTags);	
	dispatchUnit->outSystemRegisterBranchCounter(systemRegisterBranchCounter);
	dispatchUnit->inSystemRegisterBusy(systemRegisterBusy);
	completionUnit->outSystemRegisterExecute(systemRegisterExecute);
	completionUnit->outSystemRegisterExecuteTag(systemRegisterExecuteTag);
	dispatchUnit->inSystemRegisterExecute(systemRegisterExecute);
	dispatchUnit->inSystemRegisterExecuteTag(systemRegisterExecuteTag);
	systemRegisterUnit->inDispatched(systemRegisterDispatched);
	systemRegisterUnit->inOperation(systemRegisterOperation);
	systemRegisterUnit->inTags(systemRegisterTags);	
	systemRegisterUnit->outBusy(systemRegisterBusy);
	systemRegisterUnit->inBranchFinished(branchFinished);
	systemRegisterUnit->inMispredictedBranch(mispredictedBranch);
	systemRegisterUnit->inBranchCounter(systemRegisterBranchCounter);
	
#if defined(DEBUG) || defined(TRACE)
	dispatchUnit->outSystemRegisterInstructionCounter(systemRegisterInstructionCounter);
	dispatchUnit->outSystemRegisterProgramCounter(systemRegisterProgramCounter);
	dispatchUnit->outSystemRegisterInstruction(systemRegisterInstruction);
	systemRegisterUnit->inInstructionCounter(systemRegisterInstructionCounter);
	systemRegisterUnit->inProgramCounter(systemRegisterProgramCounter);
	systemRegisterUnit->inInstruction(systemRegisterInstruction);
#endif
	/* L1 Data cache */
	loadStoreUnit->outDCacheReq(lsu2dcacheReq);
	loadStoreUnit->outDCacheData(lsu2dcacheWriteData);
	loadStoreUnit->outDCacheWrite(lsu2dcacheWrite);
	loadStoreUnit->outDCacheAddr(lsu2dcacheAddr);
	loadStoreUnit->outDCacheSize(lsu2dcacheSize);
	loadStoreUnit->outDCacheZeroBlock(lsu2dcacheZeroBlock);
	dcache->inReq(lsu2dcacheReq);
	dcache->inData(lsu2dcacheWriteData);
	dcache->inWrite(lsu2dcacheWrite);
	dcache->inAddr(lsu2dcacheAddr);
	dcache->inSize(lsu2dcacheSize);
	dcache->inZeroBlock(lsu2dcacheZeroBlock);
	dcache->outAck(dcache2lsuAck);
	dcache->outData(dcache2lsuReadData);
	dcache->outHit(dcache2lsuHit);
	loadStoreUnit->inDCacheAck(dcache2lsuAck);
	loadStoreUnit->inDCacheData(dcache2lsuReadData);
	loadStoreUnit->inDCacheHit(dcache2lsuHit);
	
	dcache->outBusy(dcacheBusy);
	dispatchUnit->inDCacheBusy(dcacheBusy);
	
	/* Bus interface */	
	dcache->outMemReq(dcache2biuReq);
	dcache->outMemWrite(dcache2biuWrite);
	dcache->outMemAddr(dcache2biuAddr);
	dcache->outMemData(dcache2biuWriteData);
	busInterfaceUnit->inDCacheReq(dcache2biuReq);
	busInterfaceUnit->inDCacheWrite(dcache2biuWrite);
	busInterfaceUnit->inDCacheAddr(dcache2biuAddr);
	busInterfaceUnit->inDCacheData(dcache2biuWriteData);
	busInterfaceUnit->outDCacheAck(biu2dcacheAck);
	busInterfaceUnit->outDCacheData(biu2dcacheReadData);
	dcache->inMemAck(biu2dcacheAck);
	dcache->inMemData(biu2dcacheReadData);
	
	/* Integer unit results */
	for(i = 0; i < nIntegerUnit; i++)