dispatchunit.cpp

ppc750 system design simulator using system c

#endif
								/* Allocate a rename buffer, and store its tag into the reservation station */
								rs[i].loadStore->tags.resultTags[1] = registersBinding->AllocateRenameBuffer(dstReg);
						}
						else
						{
							/* Instruction has no destination register */
							rs[i].loadStore->tags.resultTags[1] = -1;
						}
						
						/* Store the instruction tag into the reservation station */
						rs[i].loadStore->tags.tag = rob->GetIndex(*robEntry);
						rs[i].loadStore->branchCounter = branchCounter;
						
						/* Store some other usefull informations into the reoder buffer entry */		
						robEntry->extra.loadStore.write = rs[i].loadStore->operation.write;
						robEntry->extra.loadStore.tags = rs[i].loadStore->tags;
						robEntry->branchCounter = rs[i].loadStore->branchCounter;
						robEntry->executionSerialized = false;
						robEntry->extra.loadStore.floatingPoint = rs[i].loadStore->operation.floatingPoint;
#if defined(DEBUG) || defined(TRACE)
						robEntry->dbgInstructionCounter = rs[i].loadStore->dbgInstructionCounter;
						robEntry->dbgProgramCounter = rs[i].loadStore->dbgProgramCounter;
						robEntry->dbgInstruction = rs[i].loadStore->dbgInstruction;
#endif					
					}
					break;
					
				case BranchUnitIdent:
					if(queue[i]->branchPredictedTaken)
						nBranchInstructionsToDispatch++;
					else
						nNonBranchInstructionsToDispatch++;
#ifdef DEBUG
					if(Debug(DebugDispatchUnit))
						cout << "unit : branch" << endl;
#endif
#ifdef TRACE
					if(Trace(TraceDispatchUnit))
					{
						trace_file->Value("number", instructionQueueEntry.dbgInstructionCounter);
						trace_file->Value("pc", instructionQueueEntry.pc);
						trace_file->Value("unit", "branch");
					}
#endif
					if(decodedInstructions[i].io.branch.inCR)
					{
						/* Instruction has a source CR field */
						int crf = decodedInstructions[i].io.branch.crf;
#ifdef DEBUG
						if(Debug(DebugDispatchUnit))
							cout << "source register : CR" << crf << endl;
#endif
						tag_t tag = registersBinding->GetCRRenameBuffer(crf);	/* Get the CR field rename buffer */
						rs[i].branch->cr.tag = tag;		/* and store its tag into the reservation station */
						rs[i].branch->cr.valid = false;	/* make the reservation station to wait for the rename buffer */
						
						if(tag >= 0)
						{
							/* The CR field is renamed */
							if(registersBinding->CRRenameBufferValid(tag))
							{
								/* The rename buffer yet contains the right value */
#ifdef DEBUG
								if(Debug(DebugDispatchUnit))
								{
									if(readRenameCRPort >= nReadRenameCRPorts)
									{
										cout << name() << ": not enough read CR rename buffer ports" << endl;
										ABORT();
									}
								}
#endif
								branchReadingCR[i] = -1;			/* No CR field register is being read */
								branchReadingRenameCR[i] = tag;		/* Remember that we are reading the rename buffer */
								outReadRenameCRNumber[readRenameCRPort++] = tag;	/* Ask the rename buffer value */
							}
							else
							{
								branchReadingCR[i] = -1;
								branchReadingRenameCR[i] = -1;
								/* Just wait for the value to be produced by the functional units */
							}
						}
						else
						{
							/* The CR field is not renamed */
							branchReadingCR[i] = 0;		/* Remember that we are reading CR */
							branchReadingRenameCR[i] = -1;	/* No rename buffer is being read */
						}
					}
					else
					{
						/* No source CR field */
						branchReadingCR[i] = -1;
						branchReadingRenameCR[i] = -1;
						rs[i].branch->cr.tag = -1;
					}
				
					if(decodedInstructions[i].io.branch.inLR)
					{
						/* Instruction has LR as source register */
#ifdef DEBUG
						if(Debug(DebugDispatchUnit))
							cout << "source register : LR" << endl;
#endif
						tag_t tag = registersBinding->GetLRRenameBuffer();	/* Get the rename buffer */
						rs[i].branch->lr.tag = tag;		/* and store its tag into the reservation station */
						rs[i].branch->lr.valid = false;	/* make the reservation station to wait for the rename buffer */
						
						if(tag >= 0)
						{
							/* LR is renamed */
							if(registersBinding->LRRenameBufferValid(tag))
							{
								/* The LR rename buffer yet contains the right value */
#ifdef DEBUG
								if(Debug(DebugDispatchUnit))
									if(readRenameLRPort >= nReadRenameLRPorts)
									{
										cout << name() << ": not enough read LR rename buffer ports" << endl;
										ABORT();
									}
#endif
								branchReadingLR[i] = -1;			/* Don't read LR */
								branchReadingRenameLR[i] = tag;		/* instead, read from the rename buffer */
								outReadRenameLRNumber[readRenameLRPort++] = tag;	/* Ask the rename buffer value */
							}
							else
							{
								branchReadingLR[i] = -1;
								branchReadingRenameLR[i] = -1;
								/* Just wait for the value to be produce by functional units */
							}
						}
						else
						{
							/* LR is not renamed */
							branchReadingLR[i] = 0;			/* read its value directly from the register */
							branchReadingRenameLR[i] = -1;	/* No LR rename buffer is being read */
						}
					}
					else
					{
						/* LR is not a source register */
						branchReadingLR[i] = -1;
						branchReadingRenameLR[i] = -1;
						rs[i].branch->lr.tag = -1;
					}
					
					if(decodedInstructions[i].io.branch.inCTR)
					{
						/* Instruction has CTR as source register */
#ifdef DEBUG
						if(Debug(DebugDispatchUnit))
							cout << "source register : CTR" << endl;
#endif
						tag_t tag = registersBinding->GetCTRRenameBuffer();	/* Get the CTR rename buffer */
						rs[i].branch->ctr.tag = tag;		/* and store its tag into the reservation station */
						rs[i].branch->ctr.valid = false;	/* make the reservation station to wait for the LR rename buffer */
						
						if(tag >= 0)
						{
							/* CTR is renamed */
							if(registersBinding->CTRRenameBufferValid(tag))
							{
								/* The CTR rename buffer yet contains the right value */
#ifdef DEBUG
								if(Debug(DebugDispatchUnit))
									if(readRenameCTRPort >= nReadRenameCTRPorts)
									{
										cout << name() << ": not enough read CTR rename buffer ports" << endl;
										ABORT();
									}
#endif
								branchReadingCTR[i] = -1;			/* Don't read CTR directly from the register */
								branchReadingRenameCTR[i] = tag;	/* instead, read its value from the rename buffer */
								outReadRenameCTRNumber[readRenameCTRPort++] = tag;	/* Ask for the rename buffer value */
							}
							else
							{
								branchReadingCTR[i] = -1;
								branchReadingRenameCTR[i] = -1;
								/* Just wait for the value to be produced by functional units */
							}
						}
						else
						{
							branchReadingCTR[i] = 0;		/* read the CTR value directly from the register */
							branchReadingRenameCTR[i] = -1;	/* No rename buffer is being read */
						}
					}
					else
					{
						/* CTR is not a source register for that instruction */
						branchReadingCTR[i] = -1;
						branchReadingRenameCTR[i] = -1;
						rs[i].branch->ctr.tag = -1;
					}			
					
					/* Store the branch operation into the reservation station */
					rs[i].branch->operation = decodedInstructions[i].operation.branch;
#if defined(DEBUG) || defined(TRACE)
					{
						const InstructionQueueEntry& instructionQueueEntry = *queue[i];
						rs[i].branch->dbgInstructionCounter = instructionQueueEntry.dbgInstructionCounter;
						rs[i].branch->dbgInstruction = instructionQueueEntry.instruction;
					}
#endif

					/* Store the immediate value into the reservation station */
					if(decodedInstructions[i].hasImmed)
						rs[i].branch->immed = decodedInstructions[i].immed;			
									
					/* Get the tags of the destination registers, and store them into the reservation stattion */
					rs[i].branch->tags.LRTag = decodedInstructions[i].io.branch.outLR ? registersBinding->AllocateLRRenameBuffer() : -1;
					rs[i].branch->tags.CTRTag = decodedInstructions[i].io.branch.outCTR ? registersBinding->AllocateCTRRenameBuffer() : -1;
					
					{
						const InstructionQueueEntry& instructionQueueEntry = *queue[i];
						rs[i].branch->branchPredictedTaken = instructionQueueEntry.branchPredictedTaken;
						rs[i].branch->pc = instructionQueueEntry.pc;
					}

					/* Store the instruction tag into the reservation station */
					rs[i].branch->tags.tag = robEntry ? rob->GetIndex(*robEntry) : -1;
					
					/* Store some other usefull informations into the reorder buffer entry */
					rs[i].branch->branchCounter = branchCounter;
					branchCounter++;								

					if(robEntry)
					{
						robEntry->extra.branch.tags = rs[i].branch->tags;
						robEntry->branchCounter = rs[i].branch->branchCounter;
						robEntry->executionSerialized = false;
#if defined(DEBUG) || defined(TRACE)
						robEntry->dbgInstructionCounter = rs[i].branch->dbgInstructionCounter;
						robEntry->dbgProgramCounter = rs[i].branch->pc;
						robEntry->dbgInstruction = rs[i].branch->dbgInstruction;				
#endif
					}
					break;				
					
				case SystemRegisterUnitIdent:
					nNonBranchInstructionsToDispatch++;
#ifdef DEBUG
					if(Debug(DebugDispatchUnit))
						cout << "unit : System register" << endl;
#endif
#ifdef TRACE
					if(Trace(TraceDispatchUnit))
					{
						trace_file->Value("number", instructionQueueEntry.dbgInstructionCounter);
						trace_file->Value("pc", instructionQueueEntry.pc);
						trace_file->Value("unit", "system register");
					}
#endif
					/* Store the system register unit operation into the reservation station */
					rs[i].systemRegister->operation = decodedInstructions[i].operation.systemRegister;
					rs[i].systemRegister->branchCounter = branchCounter;
#if defined(DEBUG) || defined(TRACE)
					{
						const InstructionQueueEntry& instructionQueueEntry = *queue[i];
						rs[i].systemRegister->dbgInstructionCounter = instructionQueueEntry.dbgInstructionCounter;
						rs[i].systemRegister->dbgProgramCounter = instructionQueueEntry.pc;
						rs[i].systemRegister->dbgInstruction = instructionQueueEntry.instruction;
					}
#endif
					
					switch(decodedInstructions[i].iclass)
					{
						case ICMoveToSpr:
							{	
								if(decodedInstructions[i].io.mtspr.dstSpr == 8)
								{
									/* LR is a destination register for that instruction */
#ifdef DEBUG
									if(Debug(DebugDispatchUnit))
										cout << "destination register : LR" << endl;
#endif
									/* Allocate a LR rename buffer, and store its tag into the reservation station */
									rs[i].systemRegister->tags.LRTag = registersBinding->AllocateLRRenameBuffer();
								}
								else
								{
									/* LR is not a destination register */
									rs[i].systemRegister->tags.LRTag = -1;
								}
							
								if(decodedInstructions[i].io.mtspr.dstSpr == 9)
								{
									/* CTR is a destination register for that instruction */
#ifdef DEBUG
									if(Debug(DebugDispatchUnit))
										cout << "destination register : CTR" << endl;
#endif	
									/* Allocate a CTR rename buffer, and its tag into the reservation station */
									rs[i].systemRegister->tags.CTRTag = registersBinding->AllocateCTRRenameBuffer();
								}
								else
								{
									/* CTR is not a destination register */
									rs[i].systemRegister->tags.CTRTag = -1;
								}
							
								rs[i].systemRegister->tags.resultTag = -1;	/* Instruction does not modify any general purpose registers */
								rs[i].systemRegister->tags.CRTag = -1;		/* Instruction does not modify any CR field */
								rs[i].systemRegister->interlock = false;	/* Instruction does not set interlock bit */
							}
							break;
							
						case ICMoveFromSpr:
							{					
								regnum_t dstReg = decodedInstructions[i].io.mfspr.dstReg;
								
								if(dstReg >= 0)
								{
									/* Instruction has a destination register */
#ifdef DEBUG
									if(Debug(DebugDispatchUnit))
										cout << "destination register : r" << (int) dstReg << endl;
#endif
									/* Allocate a rename buffer, and store its tag into the reservation station */
									rs[i].systemRegister->tags.resultTag = registersBinding->AllocateRenameBuffer(dstReg);
								}
								else
								{
									rs[i].systemRegister->tags.resultTag = -1;
								}
								
								rs[i].systemRegister->tags.CRTag = -1;	/* Instruction does not modify any CR field */
								rs[i].systemRegister->tags.LRTag = -1;	/* Instruction does not modify LR */
								rs[i].systemRegister->tags.CTRTag = -1;	/* Instruction does not modify CTR */
								rs[i].systemRegister->interlock = false;	/* Instruction does not set interlock bit */
							}
							break;
						
						case ICMoveFromTbr:
							{					
								regnum_t dstReg = decodedInstructions[i].io.mftb.dstReg;
								
								if(dstReg >= 0)
								{
									/* Instruction has a destination register */
#ifdef DEBUG
									if(Debug(DebugDispatchUnit))
										cout << "destination register : r" << (int) dstReg << endl;
#endif
									/* Allocate a rename buffer, and store its tag into the reservation station */
									rs[i].systemRegister->tags.resultTag = registersBinding->AllocateRenameBuffer(dstReg);
								}
								else
								{
									rs[i].systemRegister->tags.resultTag = -1;
								}
								
								rs[i].systemRegister->tags.CRTag = -1;	/* Instruction does not modify any CR field */
								rs[i].systemRegister->tags.LRTag = -1;	/* Instruction does not modify LR */
								rs[i].systemRegister->tags.CTRTag = -1;	/* Instruction does not modify CTR */
								rs[i].systemRegister->interlock = false;	/* Instruction does not set interlock bit */
							}
							break;
						
						case ICCRLogical:
							{
								/* Instruction has a destination CR field */
								regnum_t crf = decodedInstructions[i].io.crlogical.dstCrf;
#ifdef DEBUG
								if(Debug(DebugDispatchUnit))
									cout << "destination register : CR" << (int) crf << endl;
#endif
								/* Allocate a CR field rename buffer, and store its tag into the reservation station */
								rs[i].systemRegister->tags.CRTag = registersBinding->AllocateCRRenameBuffer(crf);
								rs[i].systemRegister->tags.resultTag = -1;	/* Instruction does not modify any general purpose register */
								rs[i].systemRegister->tags.LRTag = -1;		/* Instruction does not modify LR */
								rs[i].systemRegister->tags.CTRTag = -1;		/* Instr