dispatchunit.h

ppc750 system design simulator using system c

/***************************************************************************
                          DispatchUnit.h  -  Unite de dispatch
                             -------------------
    begin                : Thu Apr 5 2001
    copyright            : (C) 2001 Universite Paris Sud and CEA
    author               : Gilles Mouchard
    email                : [e-mail], gilles.mouchard@.cea.fr
 ***************************************************************************/

#ifndef __DISPATCHUNIT_H__
#define __DISPATCHUNIT_H__

#include <systemc.h>
#include <IntegerRS.h>
#include <LoadStoreRS.h>
#include <RegistersBinding.h>
#include <ReorderBuffer.h>
#include <RegisterFile.h>
#include <InstructionQueue.h>
#include <BranchRS.h>
#include <SystemRegisterRS.h>
#include <FloatingPointRS.h>

SC_MODULE(DispatchUnit)
{
	/* I/O Ports */

	sc_in<bool> inClock;
	
	/* From fetch unit */
	sc_in<InstructionQueueEntry> inIQ[nIQ];	/* Oldest instructions coming from the instruction queue */
	sc_in<int> inInstructionsInQueue;						/* Number of instructions contained into the instruction queue */
	sc_in<InstructionQueueEntry> inBranchQueue[nBranchQueueEntries];
	sc_in<int> inBranchsInQueue;
	
	/* To fetch unit */
	sc_out<int> outDispatchedInstructions;					/* Number of instructions which have been decoded and dispatched */
															/* (which have to be removed from the instruction queue) */
	sc_out<int> outDispatchedBranchs;							/* Number of branchs which have been decoded and dispatched */
															/* (which have to be removed from the branch queue) */
	
	/* To Register file */
	sc_out<regnum_t> outReadRegisterNumber[nReadRegisterPorts - 1];							/* Read ports (general purpose registers): register number */
	sc_out<tag_t> outReadRenameNumber[nReadRenamePorts];									/* Read ports (rename buffers): rename buffer number */
	sc_out<regnum_t> outReadFloatingPointRegisterNumber[nReadFloatingPointRegisterPorts];	/* Read Ports (floating point registers): register number */
	sc_out<tag_t> outReadFloatingPointRenameNumber[nReadFloatingPointRenamePorts];			/* Read Ports (floating point rename buffers): rename buffer number */
	
	/* From Register file */
	sc_in<UInt32> inReadRegisterData[nReadRegisterPorts - 1];								/* Read ports (general purpose registers): register value */
	sc_in<UInt32> inReadRenameData[nReadRenamePorts];										/* Read ports (rename buffers): rename buffer value */
	sc_in<UInt64> inReadFloatingPointRegisterData[nReadFloatingPointRegisterPorts];			/* Read ports (floating point registers): register value */
	sc_in<UInt64> inReadFloatingPointRenameData[nReadFloatingPointRenamePorts];				/* Read ports (floating point rename buffers): rename buffer value */
	
	/* To Condition Register */
	sc_out<tag_t> outReadRenameCRNumber[nReadRenameCRPorts];		/* Read ports (CR field rename buffers): field number */
	
	/* From Condition Register */
	sc_in<UInt8> inReadRenameCRData[nReadRenameCRPorts];			/* Read ports (CR field rename buffers): field value */
	
	/* To Link Register */
	sc_out<tag_t> outReadRenameLRNumber[nReadRenameLRPorts];		/* Read ports (LR rename buffers): rename buffer number */
	
	/* From Link Register */
	sc_in<UInt32> inReadRenameLRData[nReadRenameLRPorts];			/* Read ports (LR rename buffers): rename buffer value */
	
	/* To Count Register */
	sc_out<tag_t> outReadRenameCTRNumber[nReadRenameCTRPorts];		/* Read Ports (CTR rename buffers): rename buffer number */
		
	/* From Count Register */
	sc_in<UInt32> inReadRenameCTRData[nReadRenameCTRPorts];			/* Read Ports (CTR rename buffers): rename buffer value */
	
	sc_in<UInt32> inCR;				/* CR value */
	sc_in<UInt32> inLR;				/* LR value */
	sc_in<UInt32> inCTR;			/* CTR value */
	
	/* To/From Integer Units */
	sc_in<bool> inIntegerBusy[nIntegerUnit];						/* true if the integer unit is busy */
	
	sc_out<bool> outIntegerDispatched[nIntegerUnit];				/* true if the integer unit is starting to execute the instruction */
	sc_out<IntegerOperation> outIntegerOperation[nIntegerUnit];		/* integer operation */
	sc_out<IntegerOperands> outIntegerOperands[nIntegerUnit];		/* operands */
	sc_out<IntegerTags> outIntegerTags[nIntegerUnit];				/* tags */
	sc_out<int> outIntegerBranchCounter[nIntegerUnit];				/* number of branch instructions that the instruction depends on */
#if defined(DEBUG) || defined(TRACE)
	sc_out<UInt32> outIntegerInstructionCounter[nIntegerUnit];		/* serial number of the instruction (debugging purposes) */
	sc_out<UInt32> outIntegerProgramCounter[nIntegerUnit];			/* instruction address (debugging purposes) */
	sc_out<UInt32> outIntegerInstruction[nIntegerUnit];				/* instruction word (debugging purposes) */
#endif
	/* To/From Floating Point Units */
	sc_in<bool> inFloatingPointBusy[nFloatingPointUnits];			/* true if the floating point unit is busy */
	sc_in<bool> inFloatingPointPipelineEmpty[nFloatingPointUnits];	/* true if the floating point pipeline is empty */
	
	sc_out<bool> outFloatingPointDispatched[nFloatingPointUnits];					/* true if the floating point unit is starting to execute the instruction */
	sc_out<FloatingPointOperation> outFloatingPointOperation[nFloatingPointUnits];	/* floating point operation */
	sc_out<FloatingPointOperands> outFloatingPointOperands[nFloatingPointUnits];	/* operands */
	sc_out<FloatingPointTags> outFloatingPointTags[nFloatingPointUnits];			/* tags */
	sc_out<int> outFloatingPointBranchCounter[nFloatingPointUnits];					/* number of branch instructions that the instruction depends on */
#if defined(DEBUG) || defined(TRACE)
	sc_out<UInt32> outFloatingPointInstructionCounter[nFloatingPointUnits];	/* serial number of the instruction (debugging purposes) */
	sc_out<UInt32> outFloatingPointProgramCounter[nFloatingPointUnits];		/* instruction address (debugging purposes) */
	sc_out<UInt32> outFloatingPointInstruction[nFloatingPointUnits];		/* instruction word (debugging purposes) */
#endif	

	/* To/From load/store unit */
	sc_in<bool> inLoadStoreBusy;			/* true if the load/store unit is busy */
	sc_in<bool> inStoreQueueStalled;		/* true if no more store instruction can be issued to the load/store unit */
	sc_in<bool> inLoadQueueStalled;			/* true if no more load instruction can be issued to the load/store unit */
	
	sc_out<bool> outLoadStoreDispatched;				/* true if the loat/store unit is starting to execute the instruction */
	sc_out<LoadStoreOperation> outLoadStoreOperation;	/* load/store operation */
	sc_out<LoadStoreOperands> outLoadStoreOperands;		/* operands */
	sc_out<LoadStoreTags> outLoadStoreTags;				/* tags */
	sc_out<int> outLoadStoreBranchCounter;				/* number of branch instructions that the instruction depends on */
#if defined(DEBUG) || defined(TRACE)
	sc_out<UInt32> outLoadStoreInstructionCounter;		/* serial number of the instruction (debugging purposes) */
	sc_out<UInt32> outLoadStoreProgramCounter;			/* instruction address (debugging purposes) */
	sc_out<UInt32> outLoadStoreInstruction;				/* instruction word (debugging purposes) */
#endif	

	/* To/From Branch Unit */
	sc_in<bool> inBranchBusy;							/* true if the branch unit is busy */
	
	sc_out<bool> outBranchDispatched;					/* true if the branch unit is starting to execute the instruction */
	sc_out<BranchOperation> outBranchOperation;			/* branch operation */
	sc_out<BranchOperands> outBranchOperands;			/* operands */
	sc_out<BranchTags> outBranchTags;					/* tags */
	
	sc_in<bool> inBranchFinished;						/* true if a branch instruction has just finished */
	sc_in<bool> inMispredictedBranch;					/* true if the branch behaviour has been mispredicted */
#if defined(DEBUG) || defined(TRACE)
	sc_out<UInt32> outBranchInstructionCounter;			/* serial number of the instruction (debugging purposes) */			
	sc_out<UInt32> outBranchInstruction;				/* instruction word (debugging purposes) */
#endif
	
	/* System Register Unit */
	sc_in<bool> inSystemRegisterBusy;							/* true if system register unit is busy */
	sc_out<bool> outSystemRegisterDispatched;					/* true if the system register unit is starting to execute the instruction */
	sc_out<SystemRegisterOperation> outSystemRegisterOperation;	/* system register unit operation */
	sc_out<SystemRegisterTags> outSystemRegisterTags;			/* tags */
	sc_out<int> outSystemRegisterBranchCounter;					/* number of branch instructions that the instruction depends on */
#if defined(DEBUG) || defined(TRACE)
	sc_out<UInt32> outSystemRegisterInstructionCounter;			/* serial number of the instruction (debugging purposes) */
	sc_out<UInt32> outSystemRegisterProgramCounter;				/* instruction address (debugging purposes) */
	sc_out<UInt32> outSystemRegisterInstruction;				/* instruction word (debugging purposes) */
#endif
		
	sc_in<bool> inSystemRegisterFinished;						/* true if a system register unit instruction has just finished (so the interlock bit can be reseted) */
	
	/* Integer Units results (forwarded) */
	sc_in<bool> inIntegerResultValid[nIntegerUnit];				/* true if the integer unit produce a result */