📄 c8051f040.inc
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;
;
;
;
; FILE NAME : C8051F040.INC
; TARGET MCUs : C8051F040, 'F041, 'F042, 'F043
; DESCRIPTION : Register/bit definitions for the C8051F04x product family.
;
; REVISION 1.1
;
;---------------------------------------------------------------------------
; BYTE Registers
P0 DATA 080H ; PORT 0
SP DATA 081H ; STACK POINTER
DPL DATA 082H ; DATA POINTER - LOW BYTE
DPH DATA 083H ; DATA POINTER - HIGH BYTE
SFRPAGE DATA 084H ; PAGE SELECT
SFRNEXT DATA 085H ; STACK NEXT PAGE
SFRLAST DATA 086H ; STACK LAST PAGE
PCON DATA 087H ; POWER CONTROL
TCON DATA 088H ; TIMER CONTROL
CPT0CN DATA 088H ; COMPARATOR 0 CONTROL
CPT1CN DATA 088H ; COMPARATOR 1 CONTROL
CPT2CN DATA 088H ; COMPARATOR 2 CONTROL
TMOD DATA 089H ; TIMER MODE
CPT0MD DATA 089H ; COMPARATOR 0 MODE
CPT1MD DATA 089H ; COMPARATOR 1 MODE
CPT2MD DATA 089H ; COMPARATOR 2 MODE
TL0 DATA 08AH ; TIMER 0 - LOW BYTE
OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL
TL1 DATA 08BH ; TIMER 1 - LOW BYTE
OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION
TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL
TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
CKCON DATA 08EH ; TIMER 0/1 CLOCK CONTROL
PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL
P1 DATA 090H ; PORT 1
SSTA0 DATA 091H ; UART 0 STATUS
SFRPGCN DATA 096H ; PAGE CONTROL
CLKSEL DATA 097H ; SYSTEM CLOCK SELECT
SCON0 DATA 098H ; UART 0 CONTROL
SCON1 DATA 098H ; UART 1 CONTROL
SBUF0 DATA 099H ; UART 0 BUFFER
SBUF1 DATA 099H ; UART 1 BUFFER
SPI0CFG DATA 09AH ; SPI 0 CONFIGURATION
SPI0DAT DATA 09BH ; SPI 0 DATA
P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE
SPI0CKR DATA 09DH ; SPI 0 CLOCK RATE CONTROL
P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE
P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE
P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE
P2 DATA 0A0H ; PORT 2
EMI0TC DATA 0A1H ; EMIF TIMING CONTROL
EMI0CN DATA 0A2H ; EMIF CONTROL
EMI0CF DATA 0A3H ; EMIF CONFIGURATION
P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE
P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE
P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
IE DATA 0A8H ; INTERRUPT ENABLE
SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS
SADDR1 DATA 0A9H ; UART 1 SLAVE ADDRESS
P1MDIN DATA 0ADH ; PORT 1 INPUT MODE
P2MDIN DATA 0AEH ; PORT 2 INPUT MODE
P3MDIN DATA 0AFH ; PORT 3 INPUT MODE
P3 DATA 0B0H ; PORT 3
FLSCL DATA 0B7H ; FLASH TIMING PRESCALAR
FLACL DATA 0B7H ; FLASH ACCESS LIMIT
IP DATA 0B8H ; INTERRUPT PRIORITY
SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK
AMX2CF DATA 0BAH ; ADC 2 MUX CONFIGURATION
AMX0PRT DATA 0BDH ; ADC 0 MUX PORT PIN SELECT REGISTER
AMX0CF DATA 0BAH ; ADC 0 CONFIGURATION REGISTER
AMX0SL DATA 0BBH ; ADC 0 AND ADC 1 MODE SELECTION
AMX2SL DATA 0BBH ; ADC 2 MUX CHANNEL SELECTION
ADC0CF DATA 0BCH ; ADC 0 CONFIGURATION
ADC2CF DATA 0BCH ; ADC 2 CONFIGURATION
ADC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE
ADC2 DATA 0BEH ; ADC 2 DATA - LOW BYTE
ADC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE
SMB0CN DATA 0C0H ; SMBUS 0 CONTROL
CAN0STA DATA 0C0H ; CAN 0 STATUS
SMB0STA DATA 0C1H ; SMBUS 0 STATUS
SMB0DAT DATA 0C2H ; SMBUS 0 DATA
SMB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS
ADC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
ADC2GT DATA 0C4H ; ADC 2 GREATER-THAN REGISTER - LOW BYTE
ADC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
ADC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE
ADC2LT DATA 0C6H ; ADC 2 LESS-THAN REGISTER - LOW BYTE
ADC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
TMR2CN DATA 0C8H ; TIMER 2 CONTROL
TMR3CN DATA 0C8H ; TIMER 3 CONTROL
TMR4CN DATA 0C8H ; TIMER 4 CONTROL
P4 DATA 0C8H ; PORT 4
TMR2CF DATA 0C9H ; TIMER 2 CONFIGURATION
TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION
TMR4CF DATA 0C9H ; TIMER 4 CONFIGURATION
RCAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE
RCAP3L DATA 0CAH ; TIMER 3 CAPTURE REGISTER - LOW BYTE
RCAP4L DATA 0CAH ; TIMER 4 CAPTURE REGISTER - LOW BYTE
RCAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
RCAP3H DATA 0CBH ; TIMER 3 CAPTURE REGISTER - HIGH BYTE
RCAP4H DATA 0CBH ; TIMER 4 CAPTURE REGISTER - HIGH BYTE
TMR2L DATA 0CCH ; TIMER 2 - LOW BYTE
TMR3L DATA 0CCH ; TIMER 3 - LOW BYTE
TMR4L DATA 0CCH ; TIMER 4 - LOW BYTE
TMR2H DATA 0CDH ; TIMER 2 - HIGH BYTE
TMR3H DATA 0CDH ; TIMER 3 - HIGH BYTE
TMR4H DATA 0CDH ; TIMER 4 - HIGH BYTE
SMB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE
PSW DATA 0D0H ; PROGRAM STATUS WORD
REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
DAC0L DATA 0D2H ; DAC 0 REGISTER - LOW BYTE
DAC1L DATA 0D2H ; DAC 1 REGISTER - LOW BYTE
DAC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE
DAC1H DATA 0D3H ; DAC 1 REGISTER - HIGH BYTE
DAC0CN DATA 0D4H ; DAC 0 CONTROL
DAC1CN DATA 0D4H ; DAC 1 CONTROL
HVA0CN DATA 0D6H ; HVDA CONTROL REGISTER
PCA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL
CAN0DATL DATA 0D8H ; CAN 0 DATA - LOW BYTE
P5 DATA 0D8H ; PORT 5
PCA0MD DATA 0D9H ; PCA 0 COUNTER MODE
CAN0DATH DATA 0D9H ; CAN 0 DATA - HIGH BYTE
PCA0CPM0 DATA 0DAH ; PCA 0 MODULE 0 CONTROL
CAN0ADR DATA 0DAH ; CAN 0 ADDRESS
PCA0CPM1 DATA 0DBH ; PCA 0 MODULE 1 CONTROL
CAN0TST DATA 0DBH ; CAN 0 TEST
PCA0CPM2 DATA 0DCH ; PCA 0 MODULE 2 CONTROL
PCA0CPM3 DATA 0DDH ; PCA 0 MODULE 3 CONTROL
PCA0CPM4 DATA 0DEH ; PCA 0 MODULE 4 CONTROL
PCA0CPM5 DATA 0DFH ; PCA 0 MODULE 5 CONTROL
ACC DATA 0E0H ; ACCUMULATOR
PCA0CPL5 DATA 0E1H ; PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE
XBR0 DATA 0E1H ; CROSSBAR CONFIGURATION REGISTER 0
PCA0CPH5 DATA 0E2H ; PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE
XBR1 DATA 0E2H ; CROSSBAR CONFIGURATION REGISTER 1
XBR2 DATA 0E3H ; CROSSBAR CONFIGURATION REGISTER 2
XBR3 DATA 0E4H ; CROSSBAR CONFIGURATION REGISTER 3
EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
EIE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
ADC0CN DATA 0E8H ; ADC 0 CONTROL
ADC2CN DATA 0E8H ; ADC 2 CONTROL
P6 DATA 0E8H ; PORT 6
PCA0CPL2 DATA 0E9H ; PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE
PCA0CPH2 DATA 0EAH ; PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE
PCA0CPL3 DATA 0EBH ; PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE
PCA0CPH3 DATA 0ECH ; PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE
PCA0CPL4 DATA 0EDH ; PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE
PCA0CPH4 DATA 0EEH ; PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE
RSTSRC DATA 0EFH ; RESET SOURCE
B DATA 0F0H ; B REGISTER
EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
SPI0CN DATA 0F8H ; SPI 0 CONTROL
CAN0CN DATA 0F8H ; CAN 0 CONTROL
P7 DATA 0F8H ; PORT 7
PCA0L DATA 0F9H ; PCA 0 TIMER - LOW BYTE
PCA0H DATA 0FAH ; PCA 0 TIMER - HIGH BYTE
PCA0CPL0 DATA 0FBH ; PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE
PCA0CPH0 DATA 0FCH ; PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE
PCA0CPL1 DATA 0FDH ; PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE
PCA0CPH1 DATA 0FEH ; PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE
WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
; BIT Registers
;TCON 0x88
TF1 BIT TCON.7 ;TIMER 1 OVERFLOW FLAG
TR1 BIT TCON.6 ;TIMER 1 ON/OFF CONTROL
TF0 BIT TCON.5 ;TIMER 0 OVERFLOW FLAG
TR0 BIT TCON.4 ;TIMER 0 ON/OFF CONTROL
IE1 BIT TCON.3 ;EXT. INTERRUPT 1 EDGE FLAG
IT1 BIT TCON.2 ;EXT. INTERRUPT 1 TYPE
IE0 BIT TCON.1 ;EXT. INTERRUPT 0 EDGE FLAG
IT0 BIT TCON.0 ;EXT. INTERRUPT 0 TYPE
;CPT0CN 0x88
CP0EN BIT CPT0CN.7 ;COMPARATOR 0 ENABLE
CP0OUT BIT CPT0CN.6 ;COMPARATOR 0 OUTPUT
CP0RIF BIT CPT0CN.5 ;COMPARATOR 0 RISING EDGE INTERRUPT
CP0FIF BIT CPT0CN.4 ;COMPARATOR 0 FALLING EDGE INTERRUPT
CP0HYP1 BIT CPT0CN.3 ;COMPARATOR 0 POSITIVE HYSTERESIS 1
CP0HYP0 BIT CPT0CN.2 ;COMPARATOR 0 POSITIVE HYSTERESIS 0
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