fq_divider.rpt

能够实现0~99的任意分频,并实现输出频率50％的占空比

-- Node name is '~2294~2' 
-- Equation name is '~2294~2', location is LC3_A7, type is buried.
-- synthesized logic cell 
_LC3_A7  = LCELL( _EQ107);
  _EQ107 =  CNT18
         #  CNT19
         #  CNT110
         #  CNT111;

-- Node name is '~2294~3' 
-- Equation name is '~2294~3', location is LC1_A2, type is buried.
-- synthesized logic cell 
_LC1_A2  = LCELL( _EQ108);
  _EQ108 =  _LC3_A2
         #  _LC3_A7
         #  CNT16
         #  CNT17;

-- Node name is '~2294~4' 
-- Equation name is '~2294~4', location is LC8_A14, type is buried.
-- synthesized logic cell 
_LC8_A14 = LCELL( _EQ109);
  _EQ109 =  CNT128
         #  CNT129
         #  CNT130
         #  CNT131;

-- Node name is '~2294~5' 
-- Equation name is '~2294~5', location is LC4_A20, type is buried.
-- synthesized logic cell 
_LC4_A20 = LCELL( _EQ110);
  _EQ110 =  CNT124
         #  CNT125
         #  CNT126
         #  CNT127;

-- Node name is '~2294~6' 
-- Equation name is '~2294~6', location is LC2_A13, type is buried.
-- synthesized logic cell 
_LC2_A13 = LCELL( _EQ111);
  _EQ111 =  CNT120
         #  CNT121
         #  CNT122
         #  CNT123;

-- Node name is '~2294~7' 
-- Equation name is '~2294~7', location is LC3_A21, type is buried.
-- synthesized logic cell 
_LC3_A21 = LCELL( _EQ112);
  _EQ112 =  CNT116
         #  CNT117
         #  CNT118
         #  CNT119;

-- Node name is '~2294~8' 
-- Equation name is '~2294~8', location is LC1_A20, type is buried.
-- synthesized logic cell 
_LC1_A20 = LCELL( _EQ113);
  _EQ113 =  _LC8_A14
         #  _LC4_A20
         #  _LC2_A13
         #  _LC3_A21;

-- Node name is '~2294~9' 
-- Equation name is '~2294~9', location is LC1_B20, type is buried.
-- synthesized logic cell 
_LC1_B20 = LCELL( _EQ114);
  _EQ114 =  CNT212
         #  CNT213
         #  CNT214
         #  CNT215;

-- Node name is '~2294~10' 
-- Equation name is '~2294~10', location is LC2_B23, type is buried.
-- synthesized logic cell 
_LC2_B23 = LCELL( _EQ115);
  _EQ115 =  CNT28
         #  CNT29
         #  CNT210
         #  CNT211;

-- Node name is '~2294~11' 
-- Equation name is '~2294~11', location is LC2_B17, type is buried.
-- synthesized logic cell 
_LC2_B17 = LCELL( _EQ116);
  _EQ116 =  _LC1_B20
         #  _LC2_B23
         #  CNT26
         #  CNT27;

-- Node name is '~2294~12' 
-- Equation name is '~2294~12', location is LC1_C1, type is buried.
-- synthesized logic cell 
_LC1_C1  = LCELL( _EQ117);
  _EQ117 =  CNT228
         #  CNT229
         #  CNT230
         #  CNT231;

-- Node name is '~2294~13' 
-- Equation name is '~2294~13', location is LC1_C9, type is buried.
-- synthesized logic cell 
_LC1_C9  = LCELL( _EQ118);
  _EQ118 =  CNT224
         #  CNT225
         #  CNT226
         #  CNT227;

-- Node name is '~2294~14' 
-- Equation name is '~2294~14', location is LC3_C2, type is buried.
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ119);
  _EQ119 =  CNT220
         #  CNT221
         #  CNT222
         #  CNT223;

-- Node name is '~2294~15' 
-- Equation name is '~2294~15', location is LC4_C3, type is buried.
-- synthesized logic cell 
_LC4_C3  = LCELL( _EQ120);
  _EQ120 =  CNT216
         #  CNT217
         #  CNT218
         #  CNT219;

-- Node name is '~2294~16' 
-- Equation name is '~2294~16', location is LC7_C9, type is buried.
-- synthesized logic cell 
_LC7_C9  = LCELL( _EQ121);
  _EQ121 =  _LC1_C1
         #  _LC1_C9
         #  _LC3_C2
         #  _LC4_C3;

-- Node name is '~2294~17' 
-- Equation name is '~2294~17', location is LC6_A19, type is buried.
-- synthesized logic cell 
_LC6_A19 = LCELL( _EQ122);
  _EQ122 = !CNT13 & !CNT15 & !CNT23 & !CNT25;

-- Node name is '~2294~18' 
-- Equation name is '~2294~18', location is LC6_A23, type is buried.
-- synthesized logic cell 
_LC6_A23 = LCELL( _EQ123);
  _EQ123 =  CNT10 & !_LC1_A2 & !_LC1_A20 &  _LC6_A19;

-- Node name is '~2294~19' 
-- Equation name is '~2294~19', location is LC3_A16, type is buried.
-- synthesized logic cell 
_LC3_A16 = LCELL( _EQ124);
  _EQ124 =  _LC5_A16 &  _LC7_A16
         #  _LC8_A16 &  _LC8_A23;

-- Node name is ':2294' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ125);
  _EQ125 = !_LC2_B17 &  _LC3_A16 &  _LC6_A23 & !_LC7_C9;

-- Node name is '~2295~1' 
-- Equation name is '~2295~1', location is LC3_A19, type is buried.
-- synthesized logic cell 
!_LC3_A19 = _LC3_A19~NOT;
_LC3_A19~NOT = LCELL( _EQ126);
  _EQ126 =  CNT14
         #  CNT11;

-- Node name is '~2295~2' 
-- Equation name is '~2295~2', location is LC5_A16, type is buried.
-- synthesized logic cell 
!_LC5_A16 = _LC5_A16~NOT;
_LC5_A16~NOT = LCELL( _EQ127);
  _EQ127 =  CNT24
         #  CNT20
         #  CNT21;

-- Node name is '~2295~3' 
-- Equation name is '~2295~3', location is LC7_A16, type is buried.
-- synthesized logic cell 
_LC7_A16 = LCELL( _EQ128);
  _EQ128 = !CNT11 & !CNT12 & !CNT14 & !CNT22;

-- Node name is '~2296~1' 
-- Equation name is '~2296~1', location is LC8_A16, type is buried.
-- synthesized logic cell 
_LC8_A16 = LCELL( _EQ129);
  _EQ129 =  CNT11 &  CNT12 &  CNT14 &  CNT24;



Project Information                            d:\maxplus\fqdiv\fq_divider.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,833K