control.c

YL9200开发板的BIOSBOX源码

#include "../inc/def.h"
#include "../inc/config.h"
#include "../inc/board.h"
#include "../inc/slib.h"
#include "../inc/utils.h"
#include "AT91RM9200.h"
#include "lib_AT91RM9200.h"

void ShowBootInfo(void)
{
	puts("\n **************************************\n");
	puts("*                                       *\n");
	puts("*     BIOS for YL9200 Board V3.00      *\n");
	puts("*        Http://www.uCdragon.com        *\n");
	puts("*                                       *\n");
	puts(" ***************************************\n");
}

static void InitBuzzer(void)
{
	int val;
	AT91PS_TC pTC = AT91C_BASE_TC2;
	
	AT91F_TC2_CfgPMC();
	pTC->TC_IDR = 0xff;	//disable all interrupts
	//select TIMER_CLOCK2 = MCK/8, CPCTRG, up mode, Waveform mode, RB compare set, RC compare clear, software trigger clear
	pTC->TC_CMR = 1|(1<<10)|(2<<13)|(1<<15)|(1<<24)|(2<<26)|(2UL<<30);	//must not set EEVT as TIOB!
	val = (AT91F_PMC_GetMasterClock(AT91C_BASE_PMC, AT91C_BASE_CKGR, 32768)>>3)/2100;
	pTC->TC_RB  = val>>1;
	pTC->TC_RC  = val;
	pTC->TC_CCR = 5;	//enable timer-counter and trig it
}

void PortInit(void)
{
	// Open PIO for DBGU
	AT91F_DBGU_CfgPIO();
	
	//led
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOB, AT91C_PIO_PB8|AT91C_PIO_PB15|AT91C_PIO_PB16|AT91C_PIO_PB17);
	//AT91F_PIO_ClearOutput(AT91C_BASE_PIOB, AT91C_PIO_PB8|AT91C_PIO_PB15|AT91C_PIO_PB16|AT91C_PIO_PB17);
	AT91F_PIO_SetOutput(AT91C_BASE_PIOB, AT91C_PIO_PB8|AT91C_PIO_PB15|AT91C_PIO_PB16|AT91C_PIO_PB17);
	//key
	AT91F_PIO_CfgInput(AT91C_BASE_PIOA, AT91C_PIO_PA24);
	AT91F_PIO_CfgInput(AT91C_BASE_PIOB, AT91C_PIO_PB1|AT91C_PIO_PB2|AT91C_PIO_PB6);
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOB, AT91C_PIO_PB7);
	AT91F_PIO_ClearOutput(AT91C_BASE_PIOB, AT91C_PIO_PB7);
	//buzzer
	InitBuzzer();
	//nand flash SMOE, SMWE
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOC, // PIO controller base address
		(unsigned int) AT91C_PC1_BFRDY_SMOE | (unsigned int) AT91C_PC3_BFBAA_SMWE,	// Peripheral A
		0);	// Peripheral B	
	//Enable PIOC clock for input, PC14->nBusy, PC15->SMCE
	AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, (U32)((1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB) | (1 << AT91C_ID_PIOC)));
	AT91F_PIO_CfgInput (AT91C_BASE_PIOC, AT91C_PIO_PC14);
	AT91F_PIO_CfgPullup(AT91C_BASE_PIOC, AT91C_PIO_PC14);
	AT91F_PIO_CfgOutput (AT91C_BASE_PIOC, AT91C_PIO_PC15);
//	AT91F_PIO_GetInput(AT91C_BASE_PIOC) & AT91C_PIO_PC14;

	//IIC	
	AT91F_TWI_CfgPIO ();
	AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, (unsigned int) AT91C_PA25_TWD);
}

void Beep(U32 freq, U32 ms)
{
	int val;
	AT91PS_TC pTC = AT91C_BASE_TC2;
	
	val = (AT91F_PMC_GetMasterClock(AT91C_BASE_PMC, AT91C_BASE_CKGR, 32768)>>3)/freq;
	if(val>65535)
		val = 65535;
	if(val<2)
		val = 2;
	pTC->TC_RB  = val>>1;
	pTC->TC_RC  = val;
	pTC->TC_CCR = 5;	//enable timer-counter and trig it

	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOA,	// PIO controller base address
		0,					// Peripheral A
		AT91C_PA22_TIOB2);	// Peripheral B
	Delay(ms);
	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PIO_PA22);
	//AT91F_PIO_SetOutput(AT91C_BASE_PIOA, AT91C_PIO_PA22);
	AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA22);
}

#define	LED1_ON()	AT91F_PIO_ClearOutput (AT91C_BASE_PIOB, 1<<8)
#define	LED2_ON()	AT91F_PIO_ClearOutput (AT91C_BASE_PIOB, 1<<15)
#define	LED3_ON()	AT91F_PIO_ClearOutput (AT91C_BASE_PIOB, 1<<16)
#define	LED4_ON()	AT91F_PIO_ClearOutput (AT91C_BASE_PIOB, 1<<17)
#define	LED1_OFF()	AT91F_PIO_SetOutput (AT91C_BASE_PIOB, 1<<8)
#define	LED2_OFF()	AT91F_PIO_SetOutput (AT91C_BASE_PIOB, 1<<15)
#define	LED3_OFF()	AT91F_PIO_SetOutput (AT91C_BASE_PIOB, 1<<16)
#define	LED4_OFF()	AT91F_PIO_SetOutput (AT91C_BASE_PIOB, 1<<17)

void LedSet(U32 LedStatus)
{
	if(LedStatus&1)
		LED1_ON();
	else
		LED1_OFF();
	
	if(LedStatus&2)
		LED2_ON();
	else
		LED2_OFF();
		
	if(LedStatus&4)
		LED3_ON();
	else
		LED3_OFF();
		
	if(LedStatus&8)
		LED4_ON();
	else
		LED4_OFF();
}

U16 GetKeyStatus(void)
{
	U16 k, r=0;
	
	k = AT91F_PIO_GetInput(AT91C_BASE_PIOB);
	if(k&(1<<1))
		r |= 1;
	if(k&(1<<2))
		r |= 2;
	if(k&(1<<6))
		r |= 4;
	if(AT91F_PIO_GetInput(AT91C_BASE_PIOA)&(1<<24))
		r |= 8;
	return r;
}

void MemCfgInit(void)
{	
	// [D15:0] pull-up
	AT91C_BASE_EBI->EBI_CFGR = (AT91C_EBI_DBPUC & 0x00) | (AT91C_EBI_EBSEN & 0x00);
	
	// Setup MEMC to support CS0=static memory, CS1=SDRAM, CS3=NAND FLASH, CS4,5,6=static memory
	AT91C_BASE_EBI->EBI_CSA = AT91C_EBI_CS0A_SMC|AT91C_EBI_CS1A_SDRAMC|AT91C_EBI_CS3A_SMC_SmartMedia|AT91C_EBI_CS4A_SMC;

	// Setup Flash 存储器参数设置CS0-CS7对应SMC2_CSR[0]-SMC2_CSR[7]
	// NOR Flash
	AT91C_BASE_SMC2->SMC2_CSR[0] = (AT91C_SMC2_NWS & 11)  | AT91C_SMC2_WSEN |
	                               (AT91C_SMC2_TDF & 0x100)| AT91C_SMC2_BAT |
	                                AT91C_SMC2_DBW_16 | AT91C_SMC2_ACSS_1_CYCLE |
	                               (AT91C_SMC2_RWSETUP & (1<<24)) | (AT91C_SMC2_RWHOLD & (2<<28));
	// IDE参数
	AT91C_BASE_SMC2->SMC2_CSR[2] = (AT91C_SMC2_NWS & 7)  | AT91C_SMC2_WSEN |
	                               (AT91C_SMC2_TDF & 0x100)| AT91C_SMC2_BAT |
	                                AT91C_SMC2_DBW_16 | AT91C_SMC2_ACSS_STANDARD |
	                               (AT91C_SMC2_RWSETUP & (0<<24)) | (AT91C_SMC2_RWHOLD & (1<<28));
	// NAND Flash
	AT91C_BASE_SMC2->SMC2_CSR[3] = (AT91C_SMC2_NWS & 5)  | AT91C_SMC2_WSEN |
	                               (AT91C_SMC2_TDF & 0x100)| AT91C_SMC2_BAT |
	                                AT91C_SMC2_DBW_8 | AT91C_SMC2_ACSS_STANDARD |
	                               (AT91C_SMC2_RWSETUP & (0<<24)) | (AT91C_SMC2_RWHOLD & (1<<28));
	// CF card
	AT91C_BASE_SMC2->SMC2_CSR[4] = (AT91C_SMC2_NWS & 11)  | AT91C_SMC2_WSEN |
	                               (AT91C_SMC2_TDF & 0x100)| AT91C_SMC2_BAT |
	                                AT91C_SMC2_DBW_16 | AT91C_SMC2_ACSS_1_CYCLE |
	                               (AT91C_SMC2_RWSETUP & (2<<24)) | (AT91C_SMC2_RWHOLD & (2<<28));

	//S1D13506
	AT91C_BASE_SMC2->SMC2_CSR[7] = (AT91C_SMC2_NWS & 5) | AT91C_SMC2_WSEN |
	                               (AT91C_SMC2_TDF & 0x100) | //AT91C_SMC2_BAT  |
	                                //AT91C_SMC2_DBW_16 | AT91C_SMC2_ACSS_1_CYCLE |
	                                AT91C_SMC2_DBW_16 | AT91C_SMC2_ACSS_STANDARD |
	                               (AT91C_SMC2_RWSETUP & (0<<24)) | (AT91C_SMC2_RWHOLD & (1<<28));


}

#include "../inc/mmu.h"

static MMU_Table mmu_table[] = {
	{0x00000000, 0x00100000, DRAM_END-SIZE_1M, RW_CB}, //inter-rom ram
//	{0x00000000, 0x00100000, (U32)__ENTRY, RW_CB}, //inter-rom ram
//!!! Important note, redirect IRQ vector to reset entry !!!
	{0x10000000, 0x1ff00000, 0x10000000, RW_NCNB}, //bank0
	{0x20000000, 0x21e00000, 0x20000000, (AP_RO|DOMAIN0|NCNB|DESC_SEC)},   //bank1-1
    {0x21f00000, 0x21f00000, 0x21f00000, RW_CB},   //bank1-2
	{0x30000000, 0x3ff00000, 0x30000000, RW_NCNB}, //bank2
	{0x40000000, 0x4ff00000, 0x40000000, RW_NCNB}, //bank3
	{0x50000000, 0x5ff00000, 0x50000000, RW_NCNB}, //bank4
	{0x60000000, 0x6ff00000, 0x60000000, RW_NCNB}, //bank5
	{0x70000000, 0x7ff00000, 0x70000000, RW_NCNB}, //bank6
	{0x80000000, 0x8ff00000, 0x80000000, RW_NCNB}, //bank7
	{0x90000000, 0xeff00000, 0x90000000, RW_FAULT},//not used	
	{0xf0000000, 0xfff00000, 0xf0000000, RW_NCNB}, //SFR
	{0, 0, 0, 0}
};

void BoardInitStart(void)
{
	//if boot form externl 16bits flash, remap, if boot form internal rom, don't use this!!!
	//AT91C_BASE_MC->MC_RCR = 1;	//remap toggle
	//MMU_Init(mmu_table);
	//memcpy((char *)(DRAM_END-SIZE_1M), (char *)__ENTRY, 0x1000);	
	memcpy((char *)(0), (char *)__ENTRY, 0x1000);
//	*(U32 *)0x38000000 = 0x1234;
//	*(U32 *)0xfffffc64 = 0x1234;
//	*(U32 *)0x38000000 = 0x4321;
		MMU_DisableDCache();
		MMU_EnableICache();
}

void BoardInitEnd(void)
{
}

void BoardPrepareRun(void)
{	
		//MMU_DisableDCache();
		//MMU_DCacheCleanInvalidateAll();
	MMU_DisableICache();
	MMU_InvalidateICache();
	MMU_DisableMMU();
	MMU_InvalidateTLB();
}

void CacheDisable(void)
{
//	MMU_DisableDCache();
//	MMU_DisableICache();
}

void CacheEnable(void)
{
//	MMU_EnableICache();
//	MMU_EnableDCache();
}

void CacheFlush(void)
{
//	MMU_DCacheCleanAll();		
//	MMU_DCacheCleanInvalidateAll();
}

//nand flash operation
#define	NAND_DAT	0x40000000
#define	NAND_ALE	0x40000040
#define	NAND_CLE	0x40400080


void NFChipSel(U32 sel)
{
	if(sel)
		AT91F_PIO_ClearOutput(AT91C_BASE_PIOC, AT91C_PIO_PC15);
	else
		AT91F_PIO_SetOutput(AT91C_BASE_PIOC, AT91C_PIO_PC15);			
}

int NFIsReady(void)
{
	return AT91F_PIO_GetInput(AT91C_BASE_PIOC)&AT91C_PIO_PC14;
}

void NFWrCmd(int cmd)
{
	*(volatile U8 *)NAND_CLE = cmd;
}

void NFWrAddr(int addr)
{
	*(volatile U8 *)NAND_ALE = addr;
}

void NFWrDat(int dat)
{
	*(volatile U8 *)NAND_DAT = dat;
}

int NFRdDat(void)
{
	return *(volatile U8 *)NAND_DAT;
}