sysinit.s

YL9200开发板的BIOSBOX源码

	INCLUDE	AT91RM9200.inc

DRAM_BASE		EQU	0x20000000
DRAM_END		EQU	0x22000000
AVAIL_DRAM_END	EQU	DRAM_END - 0x4000

;*****************************************************************   
	INCLUDE	../src/vector.s
;	AREA    reset, CODE, READONLY
;*****************************************************************
;初始化程序开始

;	EXPORT	InitSystem
InitSystem
	ldr	r0, =AT91C_BASE_CKGR	; Get the CKGR Base Address
	ldr	r1, =AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT
	str	r1, [r0, #CKGR_MOR]	;Enable Main Oscillator and set OSCOUNT
	
	ldr	r2, =AT91C_BASE_PMC
	mov	r1, #0x1000
WaitForMainOsc
	subs	r1, r1, #1
	beq	WaitForMainOscEnd
	ldr	r3, [r2, #PMC_SR]
	tst	r3, #AT91C_PMC_MOSCS	;wait for Main oscillator is stabilized
	beq	WaitForMainOsc
WaitForMainOscEnd
	mov	r1, #0x1000
LoopOsc
	subs	r1, r1, #1
	beq	LoopOscEnd
	ldr	r3, [r0, #CKGR_MCFR]
	tst	r3, #AT91C_CKGR_MAINRDY
	beq	LoopOsc
LoopOscEnd
	mov	r1, #0
	
	;ldr	r0, =AT91C_BASE_MC
	;str	r1, [r0, #MC_PUIA]
	;str	r1, [r0, #MC_PUP]
	;str	r1, [r0, #MC_PUER]
;	str	r1, [r0, #MC_ASR]		;只读,复位后为0
;	str	r1, [r0, #MC_AASR]		;只读,复位后为0
	
;	ldr	r0, =AT91C_BASE_EBI
;	str	r1, [r0, #EBI_CFGR]		;复位后值为0
	
	;Configure PIOC as peripheral (D16/D31)
	ldr	r0, =AT91C_BASE_PIOC
	mov	r1, #0x00ff0000
	orr	r1, r1, #0xff000000
	str	r1, [r0, #PIO_ASR]
	mov	r2, #0
	str	r2, [r0, #PIO_BSR]
	str	r1, [r0, #PIO_PDR]
	
	;Setup MEMC to support connected SDRAM (CS0 = FLASH, CS1=SDRAM, CS3=SmartMedia Card)
	ldr	r0, =AT91C_BASE_EBI
	mov	r1, #(AT91C_EBI_CS1A|AT91C_EBI_CS3A_SMC_SmartMedia)
	str	r1, [r0, #EBI_CSA]
	
	;Init FLASH
	ldr	r0, =AT91C_BASE_SMC2
	ldr	r1, =(AT91C_SMC2_NWS :AND: 0x4) | AT91C_SMC2_WSEN | (AT91C_SMC2_TDF :AND: 0x200) | AT91C_SMC2_BAT | AT91C_SMC2_DBW_16;
	str	r1, [r0, #SMC2_CSR]
	
	;Init clocks
	ldr	r2, =AT91C_BASE_PMC
	mov	r3, #0
	sub	r3, r3, #1				;0xffffffff
	str	r3, [r2, #PMC_IDR]		;禁止PMC的所有中断源
	
	ldr	r0, =AT91C_BASE_CKGR
	ldr	r1, =0x10483E0E			;PLLB = 0x48*18.432M/0xe = 96.109714M
	str	r1, [r0, #CKGR_PLLBR]
	mov	r1, #0x1000
WaitForPllb
	subs	r1, r1, #1
	beq	WaitForPllbEnd
	ldr	r3, [r2, #PMC_SR]
	tst	r3, #AT91C_PMC_LOCKB	;wait for Plla is locked
	beq	WaitForPllb
WaitForPllbEnd
	ldr	r3, =0x203				;将主时钟源换到PLLB
	str	r3, [r2, #PMC_MCKR]
	mov	r1, #0x1000
WaitForMck
	subs	r1, r1, #1
	beq	WaitForMckEnd
	ldr	r3, [r2, #PMC_SR]
	tst	r3, #AT91C_PMC_MCKRDY	;等待主时钟稳定
	beq	WaitForMck
WaitForMckEnd

	;Init SDRAM
	mov	r2, #0
	[ {FALSE}
	ldr	r0, =AT91C_BASE_SDRC
	ldr	r1, =0x2188c155	;最低4位 5=12x9, 9=13x9, a=13x10
	str	r1, [r0, #SDRC_CR]
	mov	r1, #2
	str	r1, [r0, #SDRC_MR]
	ldr	r3, =DRAM_BASE
	str	r2, [r3]
	mov	r1, #4
	str	r1, [r0, #SDRC_MR]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	
	mov	r1, #3
	str	r1, [r0, #SDRC_MR]
	str	r2, [r3, #0x80]
	
	mov	r1, #0x2e0
	str	r1, [r0, #SDRC_TR]
	str	r2, [r3]

	str	r2, [r0, #SDRC_MR]
	str	r2, [r3]
	|
	ldr	r0, =AT91C_BASE_SDRC
	ldr	r1, =0x2199C159	;最低4位 5=12x9, 9=13x9, a=13x10
	;ldr	r1, =0x21914159
	str	r1, [r0, #SDRC_CR]
	mov	r1, #2
	str	r1, [r0, #SDRC_MR]
	ldr	r3, =DRAM_BASE
	str	r2, [r3]
	mov	r1, #4
	str	r1, [r0, #SDRC_MR]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	str	r2, [r3]
	
	mov	r1, #3
	str	r1, [r0, #SDRC_MR]
	str	r2, [r3, #0x80]
	
	mov	r1, #0x1D8
	;mov	r1, #528
	str	r1, [r0, #SDRC_TR]
	str	r2, [r3]

	str	r2, [r0, #SDRC_MR]
	str	r2, [r3]
	]

;设置IQR处理程序入口, 在配置好RAM后设置	
	;ldr	r0, =IrqSvcVector	
	;ldr	r1, =IRQ_SERVICE		
	;str	r1, [r0]			;在copy完后设置
	
;----------------------------------------
; Read/modify/write CP15 control register 
;----------------------------------------
;	MRC     p15, 0, r0, c1, c0,0 ; read cp15 control registre (cp15 r1) in r0
;	ldr     r3, =0xC0000080      ; Reset bit :Little Endian end fast bus mode
;	ldr     r4, =0xC0000000      ; Set bit :Asynchronous clock mode, Not Fast Bus
;	BIC     r0, r0, r3             
;	ORR     r0, r0, r4             
;	MCR     p15, 0, r0, c1, c0,0 ; write r0 in cp15 control registre (cp15 r1)
	
	b	InitSystem_exit
	
;***********************************************
	EXPORT	IRQ_SERVICE 
IRQ_SERVICE
	sub	sp, sp, #4       ;reserved for PC
	stmfd	sp!,{r8-r9}
	
	ldr	r9, =AT91C_BASE_AIC
	mov	r8, r9
	ldr	r9, [r9, #AIC_ISR]
	and	r9, r9, #0x1f
	add	r8, r8, r9, lsl #2
	ldr	r8, [r8, #AIC_SVR]
	str	r8, [sp, #8]
	ldmfd	sp!,{r8-r9,pc}	
	
;***********************************************
;	EXPORT	IrqHandlerTab
;IrqHandlerTab	DCD	HandleADC

;***********************************************

	AREA RamData, DATA, READWRITE

	^	(AVAIL_DRAM_END - 0x800)
UserStack	#	256
SVCStack	#	256
UndefStack	#	256
AbortStack	#	256
IRQStack	#	256
FIQStack	#	256
	EXPORT	UserStack
	EXPORT	SVCStack
	EXPORT	UndefStack
	EXPORT	AbortStack
	EXPORT	IRQStack
	EXPORT	FIQStack

	MAP	(AVAIL_DRAM_END - 0x100)
SysRstVector	#	4	
UdfInsVector	#	4	
SwiSvcVector	#	4
InsAbtVector	#	4
DatAbtVector	#	4
ReservedVector	#	4
IrqSvcVector	#	4
FiqSvcVector	#	4
	EXPORT	SysRstVector
	EXPORT	UdfInsVector
	EXPORT	SwiSvcVector
	EXPORT	InsAbtVector
	EXPORT	DatAbtVector
	EXPORT	ReservedVector
	EXPORT	IrqSvcVector
	EXPORT	FiqSvcVector
	
	MAP	(AVAIL_DRAM_END - 0xe0)

;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
			
HandleADC		#	4
HandleRTC		#	4
HandleUTXD1		#	4
HandleUTXD0		#	4
HandleSIO		#	4
HandleIIC		#	4
HandleURXD1		#	4
HandleURXD0		#	4
HandleTIMER5	#	4
HandleTIMER4	#	4
HandleTIMER3	#	4
HandleTIMER2	#	4
HandleTIMER1	#	4
HandleTIMER0	#	4
HandleUERR01	#	4
HandleWDT		#	4
HandleBDMA1		#	4
HandleBDMA0		#	4
HandleZDMA1		#	4
HandleZDMA0		#	4
HandleTICK		#	4
HandleEINT4567	#	4
HandleEINT3		#	4
HandleEINT2		#	4
HandleEINT1		#	4
HandleEINT0		#	4

	MAP	(AVAIL_DRAM_END - 0x20)
pIrqStart		#	4
pIrqHandler		#	4
pIrqFinish		#	4
	EXPORT	pIrqStart
	EXPORT	pIrqHandler
	EXPORT	pIrqFinish

;****************************************************************************
	
	END