can_hw.c.bak

can bus 源代码

  ch     = ch;                        /* To avoid compiler warning           */
                                      /* "unreferenced parameter"            */

  /* Acceptance Filter Memory full                                           */
  if ((((CAN_std_cnt + 1) >> 1) + CAN_ext_cnt) >= 512)
    return CAN_OBJECTS_FULL_ERROR;

  /* Setup Acceptance Filter Configuration                                   
     Acceptance Filter Mode Register = Off                                   */
  ptrcan_af->AFMR = 0x00000001;

  /* Initialize masks for first call of function                             */
  if (CAN_std_cnt == 0 && CAN_ext_cnt == 0)  {
    ptrcan_afram->mask[0] = 0xF7FF0000; /* For std identifier pairing        */
    ptrcan_afram->mask[1] = 0xFFFFFFFF; /* For ext identifier sorting        */
    CAN_std_cnt = 1;
    CAN_ext_cnt = 1;
  }

  if (format == STANDARD_FORMAT)  {   /* Add mask for standard identifiers   */
    id |= ctrl << 13;                 /* Add controller number               */
    id &= 0x0000F7FF;                 /* Mask out 16-bits of ID              */

    cnt1 = 0;
    bound1 = (CAN_std_cnt + 1) >> 1;  /* "x >> 1" = "x / 2"                  */
    while (cnt1 < bound1)  {          /* Loop through standard existing masks  */
      if ((ptrcan_afram->mask[cnt1] >> 16) > id)  {
        cnt2 = cnt1 * 2;
        break;
      }
      if ((ptrcan_afram->mask[cnt1] & 0x0000F7FF) > id)  {
        cnt2 = cnt1 * 2 + 1;
        break;
      }
      cnt1++;                         /* cnt1 = U32 where to insert new mask */
    }                                 /* cnt2 = U16 where to insert new mask */

    buf0 = ptrcan_afram->mask[cnt1];  /* Remember current entry              */

    if ((cnt2 & 0x0001) == 0)  {      /* Insert new mask to even address     */
      buf1 = id << 16 | buf0 >> 16;
    }  else  {                        /* Insert new mask to odd address      */
      buf1 = buf0 & 0xF7FF0000 | id;
    }
    ptrcan_afram->mask[cnt1] = buf1;  /* Insert mask                         */

    CAN_std_cnt++;

    /* Even number of standard masks, no extended masks moving needed        */
    if ((CAN_std_cnt & 0x0001) == 0)  {
      bound1 = CAN_std_cnt - 2;
      /* Move all remaining standard mask entries one place up               */
      while (cnt2 < bound1)  {
        cnt1++;
        cnt2++;
        cnt2++;
        buf1 = ptrcan_afram->mask[cnt1];
        ptrcan_afram->mask[cnt1] = buf1 >> 16 | buf0 << 16;
        buf0 = buf1;
      }
    }  else  {                        /* Odd number of standard masks        */
      bound1 = CAN_std_cnt;
      /* Move all remaining standard mask entries one place up               */
      while (cnt2 < bound1)  {
        cnt1++;
        cnt2++;
        cnt2++;
        buf1 = ptrcan_afram->mask[cnt1];
        ptrcan_afram->mask[cnt1] = 0x0000F7FF | buf0 << 16;
        buf0 = buf1;
      }

      bound1 = ((CAN_std_cnt + 1) >> 1) + CAN_ext_cnt;
      /* Move all remaining extended mask entries one place up               */
      while (cnt1 < bound1)  {
        cnt1++;
        buf1 = ptrcan_afram->mask[cnt1];
        ptrcan_afram->mask[cnt1] = buf0;
        buf0 = buf1;
      }        
    }
  }  else  {                          /* Add mask for extended identifiers   */
    id |= (ctrl) << 29;               /* Add controller number               */

    cnt1 = ((CAN_std_cnt + 1) >> 1);
    cnt2 = 0;
    while (cnt2 < CAN_ext_cnt)  {     /* Loop through extended existing masks  */
      if (ptrcan_afram->mask[cnt1] > id)
        break;
      cnt1++;                         /* cnt1 = U32 where to insert new mask */
      cnt2++;
    }

    buf0 = ptrcan_afram->mask[cnt1];  /* Remember current entry              */
    ptrcan_afram->mask[cnt1] = id;    /* Insert mask                         */

    CAN_ext_cnt++;

    bound1 = CAN_ext_cnt - 1;
    /* Move all remaining extended mask entries one place up                 */
    while (cnt2 < bound1)  {
      cnt1++;
      cnt2++;
      buf1 = ptrcan_afram->mask[cnt1];
      ptrcan_afram->mask[cnt1] = buf0;
      buf0 = buf1;
    }        
  }
  
  buf0 = ((CAN_std_cnt == 0) + (CAN_std_cnt + 1) / 2) * 4;
  buf1 = buf0 + CAN_ext_cnt * 4;

  /* Setup acceptance filter pointers                                        */
  ptrcan_af->SFF_sa     = 0;
  ptrcan_af->SFF_GRP_sa = buf0;
  ptrcan_af->EFF_sa     = buf0;
  ptrcan_af->EFF_GRP_sa = buf1;
  ptrcan_af->ENDofTable = buf1;

  ptrcan_af->AFMR = 0x00000000;       /* Use acceptance filter               */

  return CAN_OK;
}

/*--------------------------- CAN_hw_tx_object ------------------------------
 *
 *  This function has no usage on LPC2xxx, and so it does nothing
 *
 *  Parameter:  ctrl:       Index of the hardware CAN controller (1 .. x)
 *              ch:         Ignorred for LPC2xxx
 *              id:         CAN message identifier
 *              CAN_FORMAT: Format of CAN identifier (standard or extended)
 *
 *  Return:     CAN_ERROR:  Error code
 *---------------------------------------------------------------------------*/

CAN_ERROR CAN_hw_tx_object (U32 ctrl, U32 ch, CAN_FORMAT format)  {
  ctrl   = ctrl;                      /* To avoid compiler warning           */
  ch     = ch;                        /* "unreferenced parameter"            */
  format = format;

  return CAN_OK;
}


#if USE_CAN_CTRL1 == 1

/*--------------------------- CAN_TX1_ISR ----------------------------------
 *
 *  CAN transmit interrupt function for controller 1
 *  If there are messages in mailbox for transmit it writes it to hardware
 *  and starts the transmission on controller 1
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_TX1_ISR (void) __irq  {
  CAN_msg *ptrmsg;
  U32 temp;

  /* Check if hardware is not beeing written to                              */
  if (wr_to_CAN_hw[0] == 0) {

    /* If there is message in mailbox ready for send, 
       read the message from mailbox and send it                             */
    if (isr_mbx_receive (MBX_tx_ctrl[0], &ptrmsg) != OS_R_OK) {
      CAN_hw_wr (1, ptrmsg);
      _free_box(CAN_mpool, ptrmsg);
    }
  }

  /* Read from interrupt register to acknowledge interrupt                   */
  temp = ptrCAN1->CANICR;
  VICVectAddr = 0;           /* Acknowledge Interrupt               */
}


/*--------------------------- CAN_RX1_ISR -----------------------------------
 *
 *  CAN receive interrupt function, for CAN controller 1
 *  Reads message from hardware registers and puts it into receive mailbox
 *  for controller 1
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_RX1_ISR (void) __irq  {
  CAN_msg *ptrmsg;

  /* If mailbox isn't full read message from hardware and send it to message queue */
  if (os_mbx_check (MBX_rx_ctrl[0]) > 0) {
    ptrmsg = _alloc_box (CAN_mpool);			// get memory
    CAN_hw_rd (1, ptrmsg);
    isr_mbx_send (MBX_rx_ctrl[0], ptrmsg);
  }

  ptrCAN1->CANCMR = 0x04;             /* Release receive buffer              */
  VICVectAddr = 0;           				/* Acknowledge interrupt               */
}

#endif


#if USE_CAN_CTRL2 == 1

/*--------------------------- CAN_TX2_ISR ----------------------------------
 *
 *  CAN transmit interrupt function for controller 2
 *  If there are messages in mailbox for transmit it writes it to hardware
 *  and starts the transmission on controller 2
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/
 
 
 extern		unsigned long		Can2TxInt;

static void CAN_TX2_ISR (void) __irq  
{
  CAN_msg *ptrmsg;
  U32 temp;
  
  
  
  #if(CAN_TEST_STATUS_TO_UART0)
  Can2TxInt = 0x55aa;
  PutString("Can 2 Int.\r\n\0");
  #endif

  /* Check if hardware is not beeing written to                              */
  if (wr_to_CAN_hw[1] == 0) 
  {

    /* If there is message in mailbox ready for send, 
       read the message from mailbox and send it                             */
    if (isr_mbx_receive (MBX_tx_ctrl[1], &ptrmsg) != OS_R_OK) {
      CAN_hw_wr (2, ptrmsg);
      _free_box(CAN_mpool, ptrmsg);
    }
  }

  /* Read from interrupt register to acknowledge interrupt                   */
  temp = ptrCAN2->CANICR;
  VICVectAddr = 0;           /* Acknowledge Interrupt               */
}


/*--------------------------- CAN_RX2_ISR -----------------------------------
 *
 *  CAN receive interrupt function, for CAN controller 2
 *  Reads message from hardware registers and puts it into receive mailbox
 *  for controller 2
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_RX2_ISR (void) __irq  {
  CAN_msg *ptrmsg;

  /* If mailbox isn't full read message from hardware and send it to message queue */
  if (os_mbx_check (MBX_rx_ctrl[1]) > 0) {
    ptrmsg = _alloc_box (CAN_mpool);
    CAN_hw_rd (2, ptrmsg);
    isr_mbx_send (MBX_rx_ctrl[1], ptrmsg);
  }
  
  
  Can2RxOK = 0x55aa;

  ptrCAN2->CANCMR = 0x04;             /* Release receive buffer              */
  VICVectAddr = 0;           /* Acknowledge interrupt               */
}

#endif


#if USE_CAN_CTRL3 == 1

/*--------------------------- CAN_TX3_ISR ----------------------------------
 *
 *  CAN transmit interrupt function for controller 3
 *  If there are messages in mailbox for transmit it writes it to hardware
 *  and starts the transmission on controller 3
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_TX3_ISR (void) __irq  {
  CAN_msg *ptrmsg;
  U32 temp;

  /* Check if hardware is not beeing written to                              */
  if (wr_to_CAN_hw[2] == 0) {

    /* If there is message in mailbox ready for send, 
       read the message from mailbox and send it                             */
    if (isr_mbx_receive (MBX_tx_ctrl[2], &ptrmsg) != OS_R_OK) {
      CAN_hw_wr (3, ptrmsg);
      _free_box(CAN_mpool, ptrmsg);
    }
  }

  /* Read from interrupt register to acknowledge interrupt                   */
  temp = ptrCAN3->CANICR;
  VICVectAddr = 0;           /* Acknowledge Interrupt               */
}


/*--------------------------- CAN_RX3_ISR -----------------------------------
 *
 *  CAN receive interrupt function, for CAN controller 3
 *  Reads message from hardware registers and puts it into receive mailbox
 *  for controller 3
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_RX3_ISR (void) __irq  {
  CAN_msg *ptrmsg;

  /* If mailbox isn't full read message from hardware and send it to message queue */
  if (os_mbx_check (MBX_rx_ctrl[2]) > 0) {
    ptrmsg = _alloc_box (CAN_mpool);
    CAN_hw_rd (3, ptrmsg);
    isr_mbx_send (MBX_rx_ctrl[2], ptrmsg);
  }

  ptrCAN3->CANCMR = 0x04;             /* Release receive buffer              */
  VICVectAddr = 0;           /* Acknowledge interrupt               */
}

#endif


#if USE_CAN_CTRL4 == 1

/*--------------------------- CAN_TX4_ISR ----------------------------------
 *
 *  CAN transmit interrupt function for controller 4
 *  If there are messages in mailbox for transmit it writes it to hardware
 *  and starts the transmission on controller 4
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_TX4_ISR (void) __irq  {
  CAN_msg *ptrmsg;
  U32 temp;

  /* Check if hardware is not beeing written to                              */
  if (wr_to_CAN_hw[3] == 0) {

    /* If there is message in mailbox ready for send, 
       read the message from mailbox and send it                             */
    if (isr_mbx_receive (MBX_tx_ctrl[3], &ptrmsg) != OS_R_OK) {
      CAN_hw_wr (4, ptrmsg);
      _free_box(CAN_mpool, ptrmsg);
    }
  }

  /* Read from interrupt register to acknowledge interrupt                   */
  temp = ptrCAN4->CANICR;
  VICVectAddr = 0;           /* Acknowledge Interrupt               */
}


/*--------------------------- CAN_RX4_ISR -----------------------------------
 *
 *  CAN receive interrupt function, for CAN controller 4
 *  Reads message from hardware registers and puts it into receive mailbox
 *  for controller 4
 *
 *  Parameter:  none
 *
 *  Return:     none
 *---------------------------------------------------------------------------*/

static void CAN_RX4_ISR (void) __irq  {
  CAN_msg *ptrmsg;

  /* If mailbox isn't full read message from hardware and send it to message queue */
  if (os_mbx_check (MBX_rx_ctrl[3]) > 0) {
    ptrmsg = _alloc_box (CAN_mpool);
    CAN_hw_rd (4, ptrmsg);
    isr_mbx_send (MBX_rx_ctrl[3], ptrmsg);
  }

  ptrCAN4->CANCMR = 0x04;             /* Release receive buffer              */
  VICVectAddr = 0;           /* Acknowledge interrupt               */
}

#endif


/*----------------------------------------------------------------------------
 * end of file
 *---------------------------------------------------------------------------*/