📄 can_hw.lst
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EXTERN CODE16 (os_mbx_check?T)
EXTERN CODE16 (isr_mbx_send?T)
EXTERN CODE16 (isr_mbx_receive?T)
EXTERN CODE16 (_alloc_box?T)
EXTERN CODE16 (_free_box?T)
EXTERN DATA (CAN_mpool)
EXTERN DATA (MBX_tx_ctrl)
EXTERN DATA (MBX_rx_ctrl)
EXTERN DATA (wr_to_CAN_hw)
EXTERN CODE32 (isr_mbx_receive?A)
EXTERN CODE32 (os_mbx_check?A)
EXTERN CODE32 (isr_mbx_send?A)
EXTERN CODE16 (?C?UDIV?T)
EXTERN CODE16 (?C?SDIV?T)
*** PUBLICS:
PUBLIC CAN_hw_setup?T
PUBLIC CAN_hw_init?T
PUBLIC CAN_hw_start?T
PUBLIC CAN_hw_tx_empty?T
PUBLIC CAN_hw_wr?T
PUBLIC CAN_hw_wr?A
PUBLIC CAN_hw_set?T
PUBLIC CAN_hw_rx_object?T
PUBLIC CAN_hw_tx_object?T
PUBLIC CAN_BASE
PUBLIC CAN_BIT_TIME
*** DATA SEGMENT '?DT0?CAN_hw':
00000000 CAN_BASE:
00000000 BEGIN_INIT
00000000 E0044000 DD 0xE0044000
00000004 E0048000 DD 0xE0048000
00000008 E004C000 DD 0xE004C000
0000000C E0050000 DD 0xE0050000
00000010 END_INIT
00000010 CAN_std_cnt:
00000010 BEGIN_INIT
00000010 0000 DW 0x0
00000012 END_INIT
00000012 CAN_ext_cnt:
00000012 BEGIN_INIT
00000012 0000 DW 0x0
00000014 END_INIT
*** DATA SEGMENT '?CON?CAN_hw':
00000000 CAN_BIT_TIME:
00000000 BEGIN_INIT
00000000 00000000 DD 0x0
00000004 00000000 DD 0x0
00000008 00000000 DD 0x0
0000000C 00000000 DD 0x0
00000010 0001C000 DD 0x1C000
00000014 00000000 DD 0x0
00000018 0012C000 DD 0x12C000
0000001C 00000000 DD 0x0
00000020 0023C000 DD 0x23C000
00000024 00000000 DD 0x0
00000028 0025C000 DD 0x25C000
0000002C 00000000 DD 0x0
00000030 0036C000 DD 0x36C000
00000034 00000000 DD 0x0
00000038 00000000 DD 0x0
ARM COMPILER V2.32a, CAN_hw 15/03/07 08:58:24 PAGE 14
0000003C 0048C000 DD 0x48C000
00000040 0049C000 DD 0x49C000
00000044 END_INIT
*** CODE SEGMENT '?PR?CAN_hw_setup?T?CAN_hw':
83: PINSEL1 &= 0xFFEBFFFF; /* Reset CAN1 bits */
00000000 4800 LDR R2,=0x140000
00000002 4800 LDR R0,=0xE002C004
00000004 6801 LDR R1,[R0,#0x0]
00000006 4391 BIC R1,R2
00000008 6001 STR R1,[R0,#0x0]
84: PINSEL1 |= 0x00040000; /* Set CAN1 bits to 01 */
0000000A 4800 LDR R2,=0x40000
0000000C 4800 LDR R0,=0xE002C004
0000000E 6801 LDR R1,[R0,#0x0]
00000010 4311 ORR R1,R2
00000012 6001 STR R1,[R0,#0x0]
87: *(&VICVectAddr0 + VIC_NUM_CTRL1_TX) = (unsigned long) CAN_TX1_ISR;
00000014 4900 LDR R1,=CAN_TX1_ISR?A ; CAN_TX1_ISR?A
00000016 4800 LDR R0,=0xFFFFF12C
00000018 6001 STR R1,[R0,#0x0]
88: *(&VICVectCntl0 + VIC_NUM_CTRL1_TX) = 0x20 | 20;
0000001A 2134 MOV R1,#0x34
0000001C 4800 LDR R0,=0xFFFFF22C
0000001E 6001 STR R1,[R0,#0x0]
90: *(&VICVectAddr0 + VIC_NUM_CTRL1_RX) = (unsigned long) CAN_RX1_ISR;
00000020 4900 LDR R1,=CAN_RX1_ISR?A ; CAN_RX1_ISR?A
00000022 4800 LDR R0,=0xFFFFF11C
00000024 6001 STR R1,[R0,#0x0]
91: *(&VICVectCntl0 + VIC_NUM_CTRL1_RX) = 0x20 | 26;
00000026 213A MOV R1,#0x3A
00000028 4800 LDR R0,=0xFFFFF21C
0000002A 6001 STR R1,[R0,#0x0]
93: VICIntEnable = 0x04100000; /* Enable CAN Tx1 and Rx1 Interrupt */
0000002C 4800 LDR R1,=0x4100000
0000002E 4800 LDR R0,=0xFFFFF010
00000030 6001 STR R1,[R0,#0x0]
96: PINSEL1 &= 0xFFFC3FFF; /* Reset CAN2 bits */
00000032 4800 LDR R2,=0x3C000
00000034 4800 LDR R0,=0xE002C004
00000036 6801 LDR R1,[R0,#0x0]
00000038 4391 BIC R1,R2
0000003A 6001 STR R1,[R0,#0x0]
97: PINSEL1 |= 0x00014000; /* Set CAN2 bits to 11 */
0000003C 4800 LDR R2,=0x14000
0000003E 4800 LDR R0,=0xE002C004
00000040 6801 LDR R1,[R0,#0x0]
00000042 4311 ORR R1,R2
00000044 6001 STR R1,[R0,#0x0]
100: *(&VICVectAddr0 + VIC_NUM_CTRL2_TX) = (unsigned long) CAN_TX2_ISR;
00000046 4900 LDR R1,=CAN_TX2_ISR?A ; CAN_TX2_ISR?A
00000048 4800 LDR R0,=0xFFFFF130
0000004A 6001 STR R1,[R0,#0x0]
101: *(&VICVectCntl0 + VIC_NUM_CTRL2_TX) = 0x20 | 21;
0000004C 2135 MOV R1,#0x35
0000004E 4800 LDR R0,=0xFFFFF230
00000050 6001 STR R1,[R0,#0x0]
103: *(&VICVectAddr0 + VIC_NUM_CTRL2_RX) = (unsigned long) CAN_RX2_ISR;
00000052 4900 LDR R1,=CAN_RX2_ISR?A ; CAN_RX2_ISR?A
00000054 4800 LDR R0,=0xFFFFF120
00000056 6001 STR R1,[R0,#0x0]
104: *(&VICVectCntl0 + VIC_NUM_CTRL2_RX) = 0x20 | 27;
00000058 213B MOV R1,#0x3B
0000005A 4800 LDR R0,=0xFFFFF220
0000005C 6001 STR R1,[R0,#0x0]
106: VICIntEnable = 0x08200000; /* Enable CAN Tx2 and Rx2 Interrupt */
ARM COMPILER V2.32a, CAN_hw 15/03/07 08:58:24 PAGE 15
0000005E 4800 LDR R1,=0x8200000
00000060 4800 LDR R0,=0xFFFFF010
00000062 6001 STR R1,[R0,#0x0]
135: return CAN_OK;
00000064 2000 MOV R0,#0x0
136: }
00000066 4770 BX R14
00000068 ENDP ; 'CAN_hw_setup?T'
*** CODE SEGMENT '?PR?CAN_calc_baudrate?T?CAN_hw':
148: static U32 CAN_calc_baudrate (U32 baudrate) {
00000000 B500 PUSH {LR}
00000002 1C03 MOV R3,R0 ; baudrate
00000004 ---- Variable 'baudrate' assigned to Register 'R3' ----
00000004 ---- Variable 'nominal_time' assigned to Register 'R2' ----
00000004 ; SCOPE-START
153: if (baudrate <= 500000) {
00000004 1C18 MOV R0,R3 ; baudrate
00000006 4800 LDR R1,=0x7A120
00000008 4288 CMP R0,R1 ; baudrate
0000000A D801 BHI L_2 ; T=0x00000010
154: nominal_time = 12;
0000000C 220C MOV R2,#0xC
155: } else if (((PCLK / 1000000) % 15) == 0) {
0000000E E000 B L_3 ; T=0x00000012
00000010 L_2:
156: nominal_time = 15;
00000010 220F MOV R2,#0xF
161: }
00000012 L_3:
164: result = (PCLK / nominal_time) / baudrate - 1;
00000012 1C11 MOV R1,R2 ; nominal_time
00000014 4800 LDR R0,=0x3938700
00000016 F7FF BL ?C?UDIV?T ; T=0x0001 (1) ; ?C?UDIV?T
00000018 FFF3 BL ?C?UDIV?T ; T=0x0001 (2) ; ?C?UDIV?T
0000001A 1C08 MOV R0,R1
0000001C 1C19 MOV R1,R3 ; baudrate
0000001E F7FF BL ?C?UDIV?T ; T=0x0001 (1) ; ?C?UDIV?T
00000020 FFEF BL ?C?UDIV?T ; T=0x0001 (2) ; ?C?UDIV?T
00000022 1C08 MOV R0,R1
00000024 3901 SUB R1,#0x1
00000026 ---- Variable 'result' assigned to Register 'R1' ----
165: result &= 0x000003FF;
00000026 4800 LDR R0,=0x3FF
00000028 4001 AND R1,R0
166: result |= CAN_BIT_TIME[nominal_time];
0000002A 1C13 MOV R3,R2 ; nominal_time
0000002C 009B LSL R3,R3,#0x2 ; nominal_time
0000002E 4800 LDR R0,=CAN_BIT_TIME ; CAN_BIT_TIME
00000030 58C0 LDR R0,[R0,R3]
00000032 4301 ORR R1,R0
168: return result;
00000034 1C08 MOV R0,R1 ; result
00000036 ; SCOPE-END
169: }
00000036 BC08 POP {R3}
00000038 4718 BX R3
0000003A ENDP ; 'CAN_calc_baudrate?T'
*** CODE SEGMENT '?PR?CAN_hw_init?T?CAN_hw':
182: CAN_ERROR CAN_hw_init (U32 ctrl, U32 baudrate) {
00000000 B510 PUSH {R4,LR}
00000002 ---- Variable 'baudrate' assigned to Register 'R1' ----
00000002 1C02 MOV R2,R0 ; ctrl
00000004 ---- Variable 'ctrl' assigned to Register 'R2' ----
00000004 ; SCOPE-START
183: U32 ctrl0 = ctrl-1; /* Controller index 0 .. x-1 */
00000004 1C10 MOV R0,R2 ; ctrl
ARM COMPILER V2.32a, CAN_hw 15/03/07 08:58:24 PAGE 16
00000006 3801 SUB R0,#0x1
00000008 ---- Variable 'ctrl0' assigned to Register 'R0' ----
184: regCAN_AF *ptrcan_af = CAN_AF_BASE;
00000008 4800 LDR R3,=0xE003C000
0000000A ---- Variable 'ptrcan_af' assigned to Register 'R3' ----
185: regCAN *ptrcan = (regCAN *) CAN_BASE[ctrl0];
0000000A 1C02 MOV R2,R0 ; ctrl0
0000000C 0092 LSL R2,R2,#0x2 ; ctrl0
0000000E 4800 LDR R0,=CAN_BASE ; CAN_BASE
00000010 5884 LDR R4,[R0,R2]
00000012 ---- Variable 'ptrcan' assigned to Register 'R4' ----
187: ptrcan_af->AFMR = 1; /* Disable acceptance filter */
00000012 2201 MOV R2,#0x1
00000014 1C18 MOV R0,R3 ; ptrcan_af
00000016 6002 STR R2,[R0,#0x0] ; ptrcan_af
188: ptrcan->CANMOD = 1; /* Enter reset mode */
00000018 2201 MOV R2,#0x1
0000001A 1C20 MOV R0,R4 ; ptrcan
0000001C 6002 STR R2,[R0,#0x0] ; ptrcan
189: ptrcan->CANIER = 0; /* Disable all interrupts */
0000001E 2000 MOV R0,#0x0
00000020 1C22 MOV R2,R4 ; ptrcan
00000022 6110 STR R0,[R2,#0x10]
190: ptrcan->CANGSR = 0; /* Clear status register */
00000024 2000 MOV R0,#0x0
00000026 1C22 MOV R2,R4 ; ptrcan
00000028 6090 STR R0,[R2,#0x8]
191: ptrcan->CANBTR = CAN_calc_baudrate(baudrate); /* Set bit timing */
0000002A 1C08 MOV R0,R1 ; baudrate
0000002C F7FF BL CAN_calc_baudrate?T ; T=0x0001 (1)
0000002E FFE8 BL CAN_calc_baudrate?T ; T=0x0001 (2)
00000030 1C21 MOV R1,R4 ; ptrcan
00000032 6148 STR R0,[R1,#0x14]
192: ptrcan->CANIER = 0x0603; /* Enable Tx and Rx interrupt */
00000034 4800 LDR R0,=0x603
00000036 1C21 MOV R1,R4 ; ptrcan
00000038 6108 STR R0,[R1,#0x10]
194: return CAN_OK;
0000003A 2000 MOV R0,#0x0
0000003C ; SCOPE-END
195: }
0000003C BC10 POP {R4}
0000003E BC08 POP {R3}
00000040 4718 BX R3
00000042 ENDP ; 'CAN_hw_init?T'
*** CODE SEGMENT '?PR?CAN_hw_start?T?CAN_hw':
207: CAN_ERROR CAN_hw_start (U32 ctrl) {
00000000 1C01 MOV R1,R0 ; ctrl
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