📄 main.asm
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;==========================================================================*
* File name : main.asm *
* Author: Qu Bo *
* Data: 2006.11.19*
* Version: 2.0 *
* Organization: DSP&EMC,National Key Laboratory of Power Electronics,
* Zhejiang University, Hangzhou 310027, China *
* Description : PROGRAM TO CONTROL A ELECTRIC CAR USE F2407A *
;==========================================================================*
.include "F2407.h"
.def _c_int0,SCI_INT
KP .SET 015
KI .SET 004
.bss CAPT,1
.bss COMP,1
.bss GPR0,1
.bss T1_PR,1
.bss TEMP,1
.bss SPEED_COUNT,1
.bss STACK,6
.bss TEMP_AD,1
.bss POSITION_OLD,1
.bss D_FLAG,1
;======================================================
ST0 .set 0
ST1 .set 1
;======================================================
; Context
;======================================================
ST0_save .set 060h ; saved status register ST0
ST1_save .set 061h ; saved status register ST1
ACCH .set 062h ; saved accumulator high
ACCL .set 063h ; saved accumulator low
P_hi .set 066h ; saved P high byte
P_lo .set 067h ; saved P low byte
T_save .set 068h ; saved T content
;======================================================
.text
.word #0ffffh
.word #0ffffh
.word #0ffffh
.word #0ffffh
_c_int0:
LDP #0H
SETC INTM
CLRC SXM
LACC IFR
SACL IFR
CLRC CNF
SETC OVM
LDP #WDCR>>7
SPLK #002Fh, WDCR ;Disable WD
KICK_DOG
SPLK #00h,GPR0
OUT GPR0,WSGR
LDP #SCSR1>>7
SPLK #0000000011111100B,SCSR1
LDP #IMR>>7
SPLK #0010H,IMR ;中端级2使能
;=====================================================
LDP #MCRA>>7
SPLK #1111111111000111B,MCRA ;EVA 模式(keyboard)
SPLK #1111111000011100B,MCRB ;仿真口，spi,其他I/O,C0,C5(keyboard)
SPLK #0000000000111111B,MCRC
SPLK #0000000000000000B,PADATDIR
SPLK #0000000000000000B,PBDATDIR
SPLK #0001010000000000B,PCDATDIR
SPLK #0H,PDDATDIR
SPLK #0111111000000000B,PEDATDIR
SPLK #0111110000000000B,PFDATDIR
LDP #SCICCR>>7
SPLK #027H,SCICCR
SPLK #003H,SCICTL1
SPLK #02H,SCICTL2
SPLK #0H,SCIHBAUD ;波特率为115200
SPLK #02aH,SCILBAUD
SPLK #20H,SCIPRI
SPLK #23H,SCICTL1
;=====================================================
LDP #0E1H
SPLK #0100000000000011b,ADCTRL1 ; Reset ADC module
NOP
SPLK #0011000000000011b,ADCTRL1 ; Take ADC out of reset,不受仿真悬挂影响
SPLK #4000H,ADCTRL2
SPLK #07h, MAXCONV ; Setup for 8 conversions
SPLK #3333h, CHSELSEQ1 ;#3333h ; Convert Channels 3
SPLK #3333h, CHSELSEQ2 ;#3333h ; Convert Channels 3
LDP #ADCTRL1>>7
SPLK #0100000000000000b,ADCTRL2 ;立即复位使排序器指针指到CONV00
SPLK #0010000000000000b,ADCTRL2 ;软件触发启动SEQ1
NOP
NOP
NOP
NOP
;======================================================
;EVA&EVB设置，T1做为全局定时器，定时周期20微秒，晶振20M
;======================================================
LDP #EVAIMRA>>7
SPLK #080H,EVAIMRA ;
SPLK #00H,EVAIMRB
SPLK #00H,EVAIMRC ;
SPLK #0FFFFH,EVAIFRA ;
SPLK #0H,EVAIFRB
SPLK #0H,EVAIFRC
SPLK #0041H,GPTCONA ;
SPLK #1942h,T1CON ;X/4
SPLK #3ffh,T1PR ;定时器1周期寄存器
SPLK #0,T2PR ;定时器2周期寄存器
SPLK #0,T1CNT ;定时器1计数器
SPLK #0,T2CNT ;定时器2计数器
SPLK #100,CMPR1 ;比较器1
SPLK #500,CMPR2 ;比较器2
SPLK #800,CMPR3 ;比较器3
SPLK #1010101000000000B,COMCONA ;
SPLK #0999H,ACTRA ;PWM1-6输出控制
SPLK #0FE0H,DBTCONA ;死区设置
LDP #COMP
SPLK #500,COMP
CLRC INTM
PP:
LDP #PADATDIR>>7
SPLK #0C700H,PADATDIR
LACC PADATDIR
SFR
SFR
SFR
AND #07H
LDP #TEMP
SACL TEMP
BCND PP,LT,EQ
SUB #07H
BCND PP,GT,EQ
LACC TEMP
SUB POSITION_OLD
BZ PP
LACC TEMP
SACL POSITION_OLD
CALL CUL
LDP #D_FLAG
LACC D_FLAG
BZ F_ZHUAN
CALL SEQUENCE_Z
KICK_DOG
B PP
F_ZHUAN
CALL SEQUENCE_F
B PP
;===============换相或修改占空比===================
SEQUENCE_Z
LACC POSITION_OLD
SUB #1
SFL
ADD #CAPT_DETER1
BACC
SEQUENCE_F
LACC POSITION_OLD
SUB #1
SFL
ADD #CAPT_DETER2
BACC
CAPT_DETER1:
B RISING2 ;3,6
B FALLING2 ;5,2
B FALLING1 ;3,2
B RISING1 ;1,4
B FALLING3 ;1,6
B RISING3 ;5,4
B END_RET
CAPT_DETER2:
B RISING3 ;5,4
B FALLING3 ;1,6
B RISING1 ;1,4
B FALLING1 ;3,2
B FALLING2 ;5,2
B RISING2 ;3,6
B END_RET
CAPT_DETER3:
B RISING3 ;5,4
B FALLING3 ;1,6
B RISING1 ;1,4
B FALLING1 ;3,2
B FALLING2 ;5,2
B RISING2 ;3,6
B END_RET
RISING3:
LDP #ACTRA>>7
SPLK #0E3Fh,ACTRA ;4,5 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR2
SACL CMPR3
SPLK #0000H,CMPR1
B END_RET
FALLING3:
LDP #ACTRA>>7
SPLK #03FEh,ACTRA ;1,6 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR1
SACL CMPR3
SPLK #0000H,CMPR2
B END_RET
RISING2:
LDP #ACTRA>>7
SPLK #03EFh,ACTRA ;3,6 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR2
SACL CMPR3
SPLK #0000H,CMPR1
B END_RET
FALLING2:
LDP #ACTRA>>7
SPLK #0EF3h,ACTRA ;2,5 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR1
SACL CMPR3
SPLK #0000H,CMPR2
B END_RET
RISING1:
LDP #ACTRA>>7
SPLK #0F3Eh,ACTRA ;1,4 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR1
SACL CMPR2
SPLK #0000H,CMPR3
B END_RET
FALLING1:
LDP #ACTRA>>7
SPLK #0FE3h,ACTRA ;2,3 高有效,其他输出高
NOP
NOP
NOP
NOP
LDP #COMP
LACC COMP
LDP #ACTRA>>7
SACL CMPR1
SACL CMPR2
SPLK #0000H,CMPR3
B END_RET
END_RET:
RET
CUL:
KICK_DOG
LDP #ADCTRL2>>7
SPLK #04000H,ADCTRL2
SPLK #02000H,ADCTRL2
NOP
NOP
CUL1
NOP
CLRC SXM
BIT ADCTRL2,BIT12
BCND CUL1,TC
LDP #RESULT0>>7
LACC RESULT0,10
ADD RESULT1,10
ADD RESULT2,10
ADD RESULT3,10
SFR
SFR
LDP #TEMP_AD
SACH COMP
LACC COMP
SUB #0H
BCND SCI_END,LT
SACL COMP
RET
SCI_END
SPLK #0,COMP
RET
SCI_INT
LDP #SCIRXBUF>>7
LACC SCIRXBUF
AND #00FFh
SUB #55H
BNZ Z_CON
LDP #D_FLAG
SPLK #1,D_FLAG
B W_INT1
Z_CON
LDP #SCIRXBUF>>7
LACC SCIRXBUF
AND #00FFh
SUB #0AAH
BNZ W_INT1
LDP #D_FLAG
SPLK #0,D_FLAG
CLRC INTM
RET
W_INT1
CLRC INTM
RET
.END
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