main.asm

2407的一些源代码

;==========================================================================*
* File name : main.asm *
* Author: Qu Bo *
* Data: 2006.11.19*
* Version: 2.0 *
* Organization: DSP&EMC,National Key Laboratory of Power Electronics, 
*               Zhejiang University, Hangzhou 310027, China *
* Description : PROGRAM TO CONTROL A ELECTRIC CAR USE F2407A * 
;==========================================================================*
        .bss  GPR0,1
        .bss  CMP_COUNT,1
        .bss  T_CMP1,1
        .bss  T_CMP2,1
        .bss  T_CMP3,1
        .bss  TEMP,1
        .bss  TEMP1,1
        .bss  T1_CMPR,1
        .bss  D_FLAG,1
        .bss  COUNT,1 
        .include "F2407.h" 		          ;the header file
;		.sect ".vectors"
		.def  _c_int0,T1_INT,SCI_INT,W_INT1
;======================================================
ST0				.set	0
ST1				.set	1
;======================================================
; Context
;======================================================
ST0_save 		.set	060h	 		  ; saved status register ST0
ST1_save 		.set	061h 			  ; saved status register ST1
ACCH 	 		.set	062h 			  ; saved accumulator high
ACCL     		.set	063h 			  ; saved accumulator low
P_hi     		.set	066h 			  ; saved P high byte
P_lo     		.set	067h 			  ; saved P low byte
T_save   		.set	068h 			  ; saved T content
;======================================================
; M A C R O ?Definitions
;======================================================
KICK_DOG 	.macro 				          ; Watchdog reset macro
		LDP 	#00E0h 			          ; DP-->7000h-707Fh
		SPLK 	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP 	#0h 			          ; DP-->0000h-007Fh
		.endm      
;======================================================
;系统初始化
;使能EVA,EVB,A/D模块，其他的未使能（根据要求使能）。
;====================================================== 
        .text  
        .word   #0ffffh
        .word	#0ffffh
        .word	#0ffffh
        .word	#0ffffh
_c_int0:	
        LDP     #0H
        SETC    INTM
        CLRC    SXM
        LACC    IFR
        SACL    IFR
        CLRC    CNF
        SETC    OVM
        LDP     #WDCR>>7
	    SPLK    #006Fh,	WDCR 	             ;看门狗不使能
	    KICK_DOG  
	    SPLK    #00h,	GPR0
		OUT     GPR0,	WSGR 
	    LDP     #SCSR1>>7
	    SPLK    #0000000011111100B,SCSR1      
	    LDP	    #IMR>>7
	    SPLK    #0012H,IMR                 	    
;=====================================================                   
	    LDP     #MCRA>>7
	    SPLK    #1111111111111011B,MCRA       ;EVA 模式(keyboard) 
	    SPLK    #1111111000011100B,MCRB       ;仿真口，spi,其他I/O,C0,C5(keyboard)  
	    SPLK    #0000000000111111B,MCRC       ;F2~F6 I/O(led)         
	    SPLK    #0000000000000000B,PADATDIR
	    SPLK    #0000000000000000B,PBDATDIR
	    SPLK    #0001010000000000B,PCDATDIR
	    SPLK    #0H,PDDATDIR
	    SPLK    #0111111000000000B,PEDATDIR
	    SPLK    #0111110000000000B,PFDATDIR
	    LDP     #TEMP1
	    SPLK    #0FFFFH,TEMP1
	    OUT     TEMP1,2000H
	    OUT     TEMP1,6000H
	    
ADCT:
	    LDP	  	#0E1H
        SPLK  	#0100000000000011b,ADCTRL1    ; Reset ADC module
	    NOP
	    SPLK  	#0011000000000011b,ADCTRL1    ; Take ADC out of reset,不受仿真悬挂影响
	                                          ;启动/停止模式，低优先级，最快的转换速度
	                                          ;双排序工作，禁止其他工作模式
	    SPLK  	#4000H,ADCTRL2
	    SPLK  	#07h, MAXCONV
	    SPLK  	#3333h, CHSELSEQ1 	          ; Convert Channels 3
	    SPLK    #3333h, CHSELSEQ2 	          ; Convert Channels 3
        LDP   	#ADCTRL1>>7
        SPLK  	#0100000000000000b,ADCTRL2    ;立即复位使排序器指针指到CONV00
 	    SPLK  	#0010000000000000b,ADCTRL2    ;软件触发启动SEQ1 
        NOP
        NOP
        NOP
		
		LDP     #SCICCR>>7
	    SPLK    #027H,SCICCR
	    SPLK    #003H,SCICTL1
	    SPLK    #02H,SCICTL2
	    SPLK    #0H,SCIHBAUD                  ;波特率为115200 
	    SPLK    #02aH,SCILBAUD 
	    SPLK    #20H,SCIPRI
	    SPLK    #23H,SCICTL1
;=====================================================		    
;EVA&EVB设置，T1做为全局定时器，定时周期20微秒，晶振20M
;=====================================================
	    LDP     #EVAIMRA>>7
	    SPLK    #0100H,EVAIMRA               ;
	    SPLK    #00H,EVAIMRB
	    SPLK    #00H,EVAIMRC                 ;
	    SPLK    #0FFFFH,EVAIFRA              ;
	    SPLK    #0H,EVAIFRB
	    SPLK    #0H,EVAIFRC
	    SPLK    #0041H,GPTCONA               ; 
	    SPLK    #1046h,T1CON                 ;X/4

	    SPLK    #470H,T1PR                   ;定时器1周期寄存器
	    SPLK    #0,T2PR                      ;定时器2周期寄存器
	    SPLK    #0,T1CNT                     ;定时器1计数器
	    SPLK    #0,T2CNT                     ;定时器2计数器
	    SPLK    #400H,CMPR1                  ;比较器1
	    SPLK    #400H,CMPR2                  ;比较器2
	    SPLK    #100,CMPR3                   ;比较器3
	    SPLK    #1010111000000000B,COMCONA   ;   
	    SPLK    #0999H,ACTRA                 ;PWM1-6输出控制
	    SPLK    #0FE0H,DBTCONA               ;死区设置
	    LDP 	#0E8h
		SPLK 	#0FE3h,ACTRA            ;#0F3Eh;PWM1,4 低有效，修改PWM1,4 的占空比 
		LDP     #COUNT
		SPLK    #0FH,COUNT
	    CLRC    INTM
PP:
		NOP
		NOP
	    B       PP

;===============定时器比较中断1=================
T1_INT

		LDP		#COUNT
		LACC    COUNT
		SUB     #1
		SACL    COUNT
		BNZ     RETURN 
		SPLK	#0FH,COUNT
		CALL    CUL
RETURN
        LDP		#EVAIFRA>>7
        LACC    EVAIFRA
        SACL    EVAIFRA	
        CLRC    INTM
        RET

SCI_INT

        LDP		#SCIRXBUF>>7
        LACC	SCIRXBUF
    	AND		#00FFh
    	SUB		#0AAH
		NOP
		NOP
		BNZ     Z_CON
		LDP		#0E8h
		SPLK 	#0FE3h,ACTRA   ;#0FE3h
	   ;	B       W_INT1
	    CLRC    INTM
        RET
Z_CON
        LDP		#SCIRXBUF>>7
        LACC	SCIRXBUF
    	AND		#00FFh
    	SUB		#055H
    	BNZ     W_INT1
        LDP		#0E8h
		SPLK 	#0F3Eh,ACTRA   ;#0F3Eh
		NOP
        CLRC    INTM
        RET

W_INT1
        CLRC    INTM
	    RET

CUL:
        KICK_DOG
		LDP		#ADCTRL2>>7
		SPLK	#04000H,ADCTRL2      ;复位整个ADC模块
		SPLK	#02000H,ADCTRL2      ;软件触发启动SEQ1
		NOP
		NOP
CUL1
		NOP
		CLRC    SXM
		BIT     ADCTRL2,BIT12
		BCND    CUL1,TC 
		LDP     #RESULT3>>7
		LACC    RESULT0,10
		ADD		RESULT1,10
		ADD		RESULT2,10
		ADD		RESULT3,10
		ADD		RESULT4,10
		ADD		RESULT5,10
		ADD		RESULT6,10
		ADD		RESULT7,10
		RPT		#2
		SFR
		LDP		#TEMP 
        SACH    TEMP
        LACC    TEMP
        SUB     #30H
        BCND    CUL2,LT
        LDP		#T1CMPR>>7
        SACL    CMPR1
        SACL    CMPR2
        RET
CUL2
        LDP     #T1CMPR>>7
        SPLK    #0H,CMPR1
        SPLK    #0H,CMPR2
        RET
       .END