📄 zdhw.c
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#ifndef __ZDHW_C__
#define __ZDHW_C__
#include "zdtypes.h"
#include "zdequates.h"
#include "zdapi.h"
#include "zdhw.h"
#include "zddebug.h"
#include "zd1211.h"
#include "zd1205.h"
extern struct net_device *g_dev;
extern u8 mMacMode;
extern u8 a_OSC_get_cal_int( u8 ch, u32 rate, u8 *intValue, u8 *calValue);
extern u8 *mTxOFDMType;
extern const U16 dot11A_Channel[];
extern const U16 dot11A_Channel_Amount;
u8 LastSetChannel=1;
u8 LastMacMode=0;
U32 GRF5101T[] = {
0x1A0000, //Null
0x1A0000, //Ch 1
0x1A8000, //Ch 2
0x1A4000, //Ch 3
0x1AC000, //Ch 4
0x1A2000, //Ch 5
0x1AA000, //Ch 6
0x1A6000, //Ch 7
0x1AE000, //Ch 8
0x1A1000, //Ch 9
0x1A9000, //Ch 10
0x1A5000, //Ch 11
0x1AD000, //Ch 12
0x1A3000, //Ch 13
0x1AB000 //Ch 14
};
U32 AL2210TB[] = {
0x2396c0, //;Null
0x0196c0, //;Ch 1
0x019710, //;Ch 2
0x019760, //;Ch 3
0x0197b0, //;Ch 4
0x019800, //;Ch 5
0x019850, //;Ch 6
0x0198a0, //;Ch 7
0x0198f0, //;Ch 8
0x019940, //;Ch 9
0x019990, //;Ch 10
0x0199e0, //;Ch 11
0x019a30, //;Ch 12
0x019a80, //;Ch 13
0x019b40 //;Ch 14
};
U32 M2827BF[] = {
0x0ccd4, //;Null
0x0ccd4, //;Ch 1
0x22224, //;Ch 2
0x37774, //;Ch 3
0x0ccd4, //;Ch 4
0x22224, //;Ch 5
0x37774, //;Ch 6
0x0ccd4, //;Ch 7
0x22224, //;Ch 8
0x37774, //;Ch 9
0x0ccd4, //;Ch 10
0x22224, //;Ch 11
0x37774, //;Ch 12
0x0ccd4, //;Ch 13
0x199a4 //;Ch 14
};
U32 M2827BN[] = {
0x30a03, //;Null
0x30a03, //;Ch 1
0x00a13, //;Ch 2
0x10a13, //;Ch 3
0x30a13, //;Ch 4
0x00a23, //;Ch 5
0x10a23, //;Ch 6
0x30a23, //;Ch 7
0x00a33, //;Ch 8
0x10a33, //;Ch 9
0x30a33, //;Ch 10
0x00a43, //;Ch 11
0x10a43, //;Ch 12
0x30a43, //;Ch 13
0x20a53 //;Ch 14
};
U32 M2827BF2[] = {
0x33334, //;Null
0x33334, //;Ch 1
0x08884, //;Ch 2
0x1ddd4, //;Ch 3
0x33334, //;Ch 4
0x08884, //;Ch 5
0x1ddd4, //;Ch 6
0x33334, //;Ch 7
0x08884, //;Ch 8
0x1ddd4, //;Ch 9
0x33334, //;Ch 10
0x08884, //;Ch 11
0x1ddd4, //;Ch 12
0x33334, //;Ch 13
0x26664 //;Ch 14
};
U32 M2827BN2[] = {
0x10a03, //;Null
0x10a03, //;Ch 1
0x20a13, //;Ch 2
0x30a13, //;Ch 3
0x10a13, //;Ch 4
0x20a23, //;Ch 5
0x30a23, //;Ch 6
0x10a23, //;Ch 7
0x20a33, //;Ch 8
0x30a33, //;Ch 9
0x10a33, //;Ch 10
0x20a43, //;Ch 11
0x30a43, //;Ch 12
0x10a43, //;Ch 13
0x20a53 //;Ch 14
};
U32 AL2230TB[] = {
0x03f790, 0x033331, 0x00000d, //;Null
0x03f790, 0x033331, 0x00000d, //;Ch 1
0x03f790, 0x0b3331, 0x00000d, //;Ch 2
0x03e790, 0x033331, 0x00000d, //;Ch 3
0x03e790, 0x0b3331, 0x00000d, //;Ch 4
0x03f7a0, 0x033331, 0x00000d, //;Ch 5
0x03f7a0, 0x0b3331, 0x00000d, //;Ch 6
0x03e7a0, 0x033331, 0x00000d, //;Ch 7
0x03e7a0, 0x0b3331, 0x00000d, //;Ch 8
0x03f7b0, 0x033331, 0x00000d, //;Ch 9
0x03f7b0, 0x0b3331, 0x00000d, //;Ch 10
0x03E7b0, 0x033331, 0x00000d, //;Ch 11
0x03e7b0, 0x0b3331, 0x00000d, //;Ch 12
0x03f7c0, 0x033331, 0x00000d, //;Ch 13
0x03e7c0, 0x066661, 0x00000d //;Ch 14
};
U32 AL7230BTB[] = {
0x09ec04, 0x8cccc8, //;Null
0x09ec00, 0x8cccc8, //;Ch 1
0x09ec00, 0x8cccd8, //;Ch 2
0x09ec00, 0x8cccc0, //;Ch 3
0x09ec00, 0x8cccd0, //;Ch 4
0x05ec00, 0x8cccc8, //;Ch 5
0x05ec00, 0x8cccd8, //;Ch 6
0x05ec00, 0x8cccc0, //;Ch 7
0x05ec00, 0x8cccd0, //;Ch 8
0x0dec00, 0x8cccc8, //;Ch 9
0x0dec00, 0x8cccd8, //;Ch 10
0x0dec00, 0x8cccc0, //;Ch 11
0x0dec00, 0x8cccd0, //;Ch 12
0x03ec00, 0x8cccc8, //;Ch 13
0x03ec00, 0x866660 //;Ch 14
};
U32 AL7230BTB_a[] = {
0x06aff4, 0x855550, 0x47f8a2, 0x21ebfe, //;Null
0x02aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;CH 8 , 5040MHz
0x02aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;CH 12, 5060MHz
0x0aaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;CH 16, 5080MHz
0x06aff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe, //;CH 34, 5170MHz
0x06aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 36, 5180MHz
0x0eaff0, 0x800008, 0x47f8a2, 0x21ebfe, //;Ch 38, 5190MHz
0x0eaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 40, 5200MHz
0x0eaff0, 0x855558, 0x47f8a2, 0x21ebfe, //;Ch 42, 5210MHz
0x0eaff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 44, 5220MHz, current support
0x0eaff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe, //;Ch 46, 5230MHz
0x0eaff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 48, 5240MHz
0x01aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 52, 5260MHz
0x01aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 56, 5280MHz, current support
0x01aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 60, 5300MHz
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 64, 5320MHz
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 68, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 72, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 76, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 80, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 84, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 88, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 92, 5320MHz,dummy
0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 96, 5320MHz,dummy
0x03aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 100, 5500MHz
0x03aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 104, 5520MHz
0x03aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 108, 5540MHz
0x0baff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 112, 5560MHz
0x0baff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 116, 5580MHz
0x0baff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 120, 5600MHz
0x07aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 124, 5620MHz
0x07aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 128, 5640MHz
0x07aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 132, 5660MHz
0x0faff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 136, 5680MHz
0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 140, 5700MHz
0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 144, 5700MHz, dummy
0x006ff0, 0x800018, 0x47f8a2, 0x21ebfe, //;Ch 149, 5745MHz
0x006ff0, 0x855540, 0x47f8a2, 0x21ebfe, //;Ch 153, 5765MHz
0x006ff0, 0x8aaab0, 0x47f8a2, 0x21ebfe, //;Ch 157, 5785MHz
0x086ff0, 0x800018, 0x47f8a2, 0x21ebfe, //;Ch 161, 5805MHz
0x086ff0, 0x855540, 0x47f8a2, 0x21ebfe, //;Ch 165, 5825MHz
0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 168, 5825MHz,dummy
0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 172, 5825MHz,dummy
0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 176, 5825MHz,dummy
0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe, //;Ch 180, 5825MHz,dummy
0x04aff0, 0x800000, 0x47f8a2, 0x21ebf6, //;Ch 184, 4920MHz
0x04aff0, 0x855550, 0x47f8a2, 0x21ebfe, //;Ch 188, 4940MHz
0x0caff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe, //;Ch 192, 4960MHz
0x0caff0, 0x800000, 0x47f8a2, 0x21ebf6 //;Ch 196, 4980MHz
};
U32 RFMD2958t[] = {
0x1422BD, //Null
0x185D17, //Null
0x181979, //Ch 1
0x1e6666, //Ch 1
0x181989, //Ch 2
0x1e6666, //Ch 2
0x181999, //Ch 3
0x1e6666, //Ch 3
0x1819a9, //Ch 4
0x1e6666, //Ch 4
0x1819b9, //Ch 5
0x1e6666, //Ch 5
0x1819c9, //Ch 6
0x1e6666, //Ch 6
0x1819d9, //Ch 7
0x1e6666, //Ch 7
0x1819e9, //Ch 8
0x1e6666, //Ch 8
0x1819f9, //Ch 9
0x1e6666, //Ch 9
0x181a09, //Ch 10
0x1e6666, //Ch 10
0x181a19, //Ch 11
0x1e6666, //Ch 11
0x181a29, //Ch 12
0x1e6666, //Ch 12
0x181a39, //Ch 13
0x1e6666, //Ch 13
0x181a60, //Ch 14
0x1c0000 //Ch 14
};
#if 0
int HW_HTP(zd_80211Obj_t *pObj)
{
void *reg = pObj->reg;
int i, ret = 0;
U32 tmpkey, tmpvalue, regvalue, seed;
dbg_pline_1("\r\nHW_HTP Starting....");
// PHY CR Registers Read/Write Test
dbg_pline_1("\r\nPHY CR Registers Read/Write Test Starting....");
seed = pObj->GetReg(reg, ZD_TSF_LowPart);
srand(seed);
LockPhyReg(pObj);
for (i=0; i<0x0200; i+=4){
if ( (i==0x00) || ((i>=0xc8) && (i<=0xfc)) ||
((i>=0x1cc) && (i<=0x1d8)) || ((i>=0x1e0) && (i<=0x1ec))){
// Skip Read Only Register
continue;
}
tmpkey = (U8)rand();
pObj->SetReg(reg, i, tmpkey);
tmpvalue = pObj->GetReg(reg, i);
if (tmpvalue != tmpkey){
//printf("CR %x Failed (Wr: %x, Rd: %x)\n", i, tmpkey, tmpvalue);
dbg_plinew_1("\r\nCR ", i);
dbg_pline_1(" Failed ");
dbg_plineb_1("(Wr: ", (U8)tmpkey);
dbg_plineb_1(", Rd: ", (U8)tmpvalue);
dbg_pline_1(")");
UnLockPhyReg(pObj);
ret = 1;
}
else{
//printf("CR %x Success (Wr: %x, Rd: %x)\n", i, tmpkey, tmpvalue);
dbg_plinew_1("\r\nCR ", i);
dbg_pline_1(" Success ");
dbg_plineb_1("(Wr: ", (U8)tmpkey);
dbg_plineb_1(", Rd: ", (U8)tmpvalue);
dbg_pline_1(")");
}
}
UnLockPhyReg(pObj);
dbg_pline_1("\r\nPHY CR Registers Read/Write Test End");
dbg_pline_1("\r\n");
#if 1
// MAC Registers Read/Write Test
dbg_pline_1("\r\nMAC Registers Read/Write Test Starting....");
//to test 0x408, 0x410, 0x42c must set 0x418 to 0
pObj->SetReg(reg, ZD_GPI_EN, 0);
seed = pObj->GetReg(reg, ZD_TSF_LowPart);
srand(seed);
for (i=0; i<NUM_REG_MASK; i++){
tmpkey = (U32)rand();
tmpkey |= (tmpkey << 16);
tmpkey &= MacRegMaskTab[i].ReadWriteMask;
if (MacRegMaskTab[i].Address == 0x42c){
pObj->SetReg(reg, ZD_GPI_EN, 0);
}
pObj->SetReg(reg, MacRegMaskTab[i].Address, tmpkey);
tmpvalue = pObj->GetReg(reg, MacRegMaskTab[i].Address);
tmpvalue &= MacRegMaskTab[i].ReadWriteMask;
if (tmpvalue != tmpkey){
//printf("MAC %x Failed (Wr: %x, Rd: %x)\n", MacRegMaskTab[i].Address, tmpkey, tmpvalue);
dbg_plinew_1("\r\nMAC ", MacRegMaskTab[i].Address);
dbg_pline_1(" Failed ");
dbg_plinel_1("(Wr: ", tmpkey);
dbg_plinel_1(", Rd: ", tmpvalue);
dbg_pline_1(")");
ret = 2;
}
else{
//printf("MAC %x Success (Wr: %x, Rd: %x)\n", MacRegMaskTab[i].Address, tmpkey, tmpvalue);
dbg_plinew_1("\r\nMAC ", MacRegMaskTab[i].Address);
dbg_pline_1(" Success ");
dbg_plinel_1("(Wr: ", tmpkey);
dbg_plinel_1(", Rd: ", tmpvalue);
dbg_pline_1(")");
}
}
dbg_pline_1("\r\nMAC Registers Read/Write Test End");
dbg_pline_1("\r\n");
#endif
#if 0
// EEPROM Read/Write Test
dbg_pline_1("\r\nEEPROM Read/Write Testing...........");
seed = pObj->GetReg(reg, ZD_TSF_LowPart);
srand(seed);
//for (tmpvalue=0; tmpvalue<1; tmpvalue++){
{
tmpkey = (U32)rand();
tmpkey |= (tmpkey << 16);
for (i=0; i<256; i++){
//if (i == 1)
//tmpkey = 0x89;
pObj->SetReg(reg, ZD_E2P_SUBID+(i*4), tmpkey);
}
// Write to EEPROM
pObj->SetReg(reg, ZD_EEPROM_PROTECT0, 0x55aa44bb);
pObj->SetReg(reg, ZD_EEPROM_PROTECT1, 0x33cc22dd);
pObj->SetReg(reg, ZD_ROMDIR, 0x422);
// Sleep
//for (i=0; i<1000; i++)
// pObj->DelayUs(5000);
delay1ms(5);
// Reset Registers
for (i=0; i<256; i++){
pObj->SetReg(reg, ZD_E2P_SUBID+(i*4), 0);
}
// Reload EEPROM
pObj->SetReg(reg, ZD_ROMDIR, 0x424);
// Sleep
//for (i=0; i<1000; i++)
// pObj->DelayUs(5000);
delay1ms(5);
// Check if right
for (i=0; i<256; i++){
regvalue = pObj->GetReg(reg, ZD_E2P_SUBID+(i*4));
if (regvalue != tmpkey){
//printf("EEPROM Addr (%x) error (Wr: %x, Rd: %x)\n", ZD_E2P_SUBID+(i*4), tmpkey, regvalue);
dbg_plinew_1("\r\nEEPROM Addr ", ZD_E2P_SUBID+(i*4));
dbg_pline_1(" error ");
dbg_plinel_1("(Wr: ", tmpkey);
dbg_plinel_1(",Rd: ", regvalue);
dbg_pline_1(")");
ret = 3;
}
}
}
#endif
//dbg_pline_1("\r\nDigital Loopback Testing...........");
dbg_pline_1("\r\nHW_HTP End");
dbg_pline_1("\r\n");
return 0;
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