📄 s3c44b0x.s
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DCD NCACHBE0_Val
DCD NCACHBE1_Val
DCD SBUSCON_Val
ENDIF
; Memory Controller Configuration
IF MC_SETUP <> 0
MC_CFG
DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
ENDIF
; Clock Management Configuration
IF CLK_SETUP <> 0
CLK_CFG
DCD CLK_BASE
DCD PLLCON_Val
DCD CLKCON_Val
DCD CLKSLOW_Val
DCD LOCKTIME_Val
ENDIF
; I/O Configuration
IF PIO_SETUP <> 0
PIO_CFG
DCD PCONA_Val
DCD PCONB_Val
DCD PCONC_Val
DCD PCOND_Val
DCD PCONE_Val
DCD PCONF_Val
DCD PCONG_Val
DCD PUPC_Val
DCD PUPD_Val
DCD PUPE_Val
DCD PUPF_Val
DCD PUPG_Val
DCD SPUCR_Val
ENDIF
; Reset Handler
EXPORT ResetHandler
ResetHandler
IF WT_SETUP <> 0
LDR R0, =WT_BASE
LDR R1, =WTCON_Val
LDR R2, =WTDAT_Val
STR R2, [R0, #WTCNT_OFS]
STR R2, [R0, #WTDAT_OFS]
STR R1, [R0, #WTCON_OFS]
ENDIF
IF CLK_SETUP <> 0
ADR R8, CLK_CFG
LDMIA R8, {R0-R4}
STR R4, [R0, #LOCKTIME_OFS]
STR R1, [R0, #PLLCON_OFS]
STR R3, [R0, #CLKSLOW_OFS]
STR R2, [R0, #CLKCON_OFS]
ENDIF
;以下三段设置时钟控制寄存器
ldr r0,=LOCKTIME
ldr r1,=0xfff
str r1,[r0]
ldr r0,=PLLCON ;锁相环倍频设定
ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) ;设定系统主时钟频率
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7ff8 ;所有功能单元块时钟使能
str r1,[r0]
;****************************************************
;change BDMACON reset value for BDMA *
;****************************************************
ldr r0,=BDIDES0
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0]
ldr r0,=BDIDES1
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0]
IF SYS_SETUP <> 0
ADR R8, SYS_CFG
LDMIA R8, {R0-R5}
STMIA R0, {R2-R4}
STR R5, [R1]
ENDIF
IF VIM_SETUP <> 0
ldr r0, =HandleIRQ
ldr r1, =IsrIRQ
str r1, [r0]
ENDIF
IF MC_SETUP <> 0
ADR R13, MC_CFG
LDMIA R13, {R0-R12}
LDR R13, =MC_BASE
STMIA R13, {R0-R12}
ENDIF
;****************************************************
;设定存储器控制寄存器 *
;****************************************************
adr r0, ResetHandler
ldr r1, =ResetHandler
sub r0, r1, r0
ldr r1, =SMRDATA
sub r0, r1, r0
ldmia r0, {r1-r13}
ldr r0, =0x01c80000 ;BWSCON Address
stmia r0, {r1-r13}
IF PIO_SETUP <> 0
ADR R13, PIO_CFG
LDMIA R13, {R0-R12}
LDR R13, =PIO_BASE
IF PIOA_SETUP <> 0
STR R0, [R13, #PCONA_OFS]
ENDIF
IF PIOB_SETUP <> 0
STR R1, [R13, #PCONB_OFS]
ENDIF
IF PIOC_SETUP <> 0
STR R2, [R13, #PCONC_OFS]
STR R7, [R13, #PUPC_OFS]
ENDIF
IF PIOD_SETUP <> 0
STR R3, [R13, #PCOND_OFS]
STR R8, [R13, #PUPD_OFS]
ENDIF
IF PIOE_SETUP <> 0
STR R4, [R13, #PCONE_OFS]
STR R9, [R13, #PUPE_OFS]
ENDIF
IF PIOF_SETUP <> 0
STR R5, [R13, #PCONF_OFS]
STR R10,[R13, #PUPF_OFS]
ENDIF
IF PIOG_SETUP <> 0
STR R6, [R13, #PCONG_OFS]
STR R11,[R13, #PUPG_OFS]
ENDIF
IF PSPU_SETUP <> 0
STR R12,[R13, #SPUCR_OFS]
ENDIF
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
SMRDATA DATA
;*****************************************************************
; Memory configuration has to be optimized for best performance *
; The following parameter is not optimized. *
;*****************************************************************
;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
;bank0 16bit BOOT ROM SST39VF160/SST39VF320
;bank1 8bit Nand Flash K9F2808U0A/K9F5608U0A
;bank2 16bit USB1.1 PDIUSBD12
;bank3 RTL8019
;bank4 No Uesed
;bank5 No Uesed
;bank6 16bit SDRAM
;bank7 16bit SDRAM
[ BUSWIDTH=16
; DCD 0x11111111 ;Bank0=OM[1:0], Bank0~Bank7=16bit
DCD 0x11111001 ;Bank0=OM[1:0] 16bit BootRomSST39VF160/SST39VF320) :0x0
; |||||||- Bank1=8bit Nand Flash
; |||||--- Bank2=8bit PDIUSBD12
; ||||---- Bank3=16bit RTL8019
; |||----- Bank4~5=16bit No Uesd
; -------- Bank6~7=16bit SDRAM
| ;BUSWIDTH=32
DCD 0x22222220 ;Bank0=OM[1:0], Bank1~Bank7=32bit
]
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
[ BDRAMTYPE="DRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN)) ;GCS6 check the MT value in parameter.a
DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN)) ;GCS7
| ;"SDRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
]
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x10 ;SCLK power down mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
END
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