📄 s3c44b0x.s
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PCONE_OFS EQU 0x28 ; PCONE Offset
PCONF_OFS EQU 0x34 ; PCONF Offset
PCONG_OFS EQU 0x40 ; PCONG Offset
PUPC_OFS EQU 0x18 ; PUPC Offset
PUPD_OFS EQU 0x24 ; PUPD Offset
PUPE_OFS EQU 0x30 ; PUPE Offset
PUPF_OFS EQU 0x3C ; PUPF Offset
PUPG_OFS EQU 0x48 ; PUPG Offset
SPUCR_OFS EQU 0x4C ; SPUCR Offset
;// <e> I/O Configuration
PIO_SETUP EQU 0
;// <e> Port A
;// <o1.0> PA0 <0=> Output <1=> ADDR0
;// <o1.1> PA1 <0=> Output <1=> ADDR16
;// <o1.2> PA2 <0=> Output <1=> ADDR17
;// <o1.3> PA3 <0=> Output <1=> ADDR18
;// <o1.4> PA4 <0=> Output <1=> ADDR19
;// <o1.5> PA5 <0=> Output <1=> ADDR20
;// <o1.6> PA6 <0=> Output <1=> ADDR21
;// <o1.7> PA7 <0=> Output <1=> ADDR22
;// <o1.8> PA8 <0=> Output <1=> ADDR23
;// <o1.9> PA9 <0=> Output <1=> ADDR24
;// </e>
PIOA_SETUP EQU 1
PCONA_Val EQU 0x000003FF
;// <e> Port B
;// <o1.0> PB0 <0=> Output <1=> SCKE
;// <o1.1> PB1 <0=> Output <1=> CKLK
;// <o1.2> PB2 <0=> Output <1=> nSCAS/nCAS2
;// <o1.3> PB3 <0=> Output <1=> nSRAS/nCAS3
;// <o1.4> PB4 <0=> Output <1=> nWBE2/nBE2/DQM2
;// <o1.5> PB5 <0=> Output <1=> nWBE3/nBE3/DQM3
;// <o1.6> PB6 <0=> Output <1=> nGCS1
;// <o1.7> PB7 <0=> Output <1=> nGCS2
;// <o1.8> PB8 <0=> Output <1=> nGCS3
;// <o1.9> PB9 <0=> Output <1=> nGCS4
;// <o1.10> PB10 <0=> Output <1=> nGCS5
;// </e>
PIOB_SETUP EQU 1
PCONB_Val EQU 0x000007FF
;// <e> Port C
;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK
;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO
;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI
;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK
;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7
;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6
;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5
;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4
;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1
;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1
;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1
;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1
;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1
;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1
;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0
;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0
;// <h> Pull-up Resistors
;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOC_SETUP EQU 1
PCONC_Val EQU 0xAAAAAAAA
PUPC_Val EQU 0x00000000
;// <e> Port D
;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved
;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved
;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved
;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved
;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved
;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOD_SETUP EQU 1
PCOND_Val EQU 0x00000000
PUPD_Val EQU 0x00000000
;// <e> Port E
;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout
;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved
;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved
;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK
;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK
;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6
;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7
;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOE_SETUP EQU 1
PCONE_Val EQU 0x00000000
PUPE_Val EQU 0x00000000
;// <e> Port F
;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved
;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0
;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0
;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD
;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY
;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD
;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK
;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOF_SETUP EQU 1
PCONF_Val EQU 0x00000000
PUPF_Val EQU 0x00000000
;// <e> Port G
;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0
;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1
;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2
;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3
;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4
;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5
;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6
;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7
;// <h> Pull-up Resistors
;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOG_SETUP EQU 1
PCONG_Val EQU 0x00000000
PUPG_Val EQU 0x00000000
;// <e> Special Pull-up
;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.2> HZ@STOP
;// <0=> Prevoius state of PAD
;// <1=> HZ @ Stop
;// </e>
PSPU_SETUP EQU 1
SPUCR_Val EQU 0x00000004
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors
b ResetHandler ;/* for debug */
b HandlerUndef ;/* handlerUndef */
b HandlerSWI ;/* SWI interrupt handler*/
b HandlerPabort ;/* handlerPAbort */
b HandlerDabort ;/* handlerDAbort */
b . ;/* handlerReserved */
ldr pc, =HandlerIRQ
b HandlerFIQ
IF VIM_SETUP <> 0
VECTOR_BRANCH ldr pc, =HandlerEINT0 ;/*mGA H/W interrupt vector table */
ldr pc, =HandlerEINT1 ;/* */
ldr pc, =HandlerEINT2 ;/* */
ldr pc, =HandlerEINT3 ;/* */
ldr pc, =HandlerEINT4567 ;/* */
ldr pc, =HandlerTICK ;/*mGA */
b .
b .
ldr pc, =HandlerZDMA0 ;/*mGB */
ldr pc, =HandlerZDMA1 ;/* */
ldr pc, =HandlerBDMA0 ;/* */
ldr pc, =HandlerBDMA1 ;/* */
ldr pc, =HandlerWDT ;/* */
ldr pc, =HandlerUERR01 ;/*mGB */
b .
b .
ldr pc, =HandlerTIMER0 ;/*mGC */
ldr pc, =HandlerTIMER1 ;/* */
ldr pc, =HandlerTIMER2 ;/* */
ldr pc, =HandlerTIMER3 ;/* */
ldr pc, =HandlerTIMER4 ;/* */
ldr pc, =HandlerTIMER5 ;/*mGC */
b .
b .
ldr pc, =HandlerURXD0 ;/*mGD */
ldr pc, =HandlerURXD1 ;/* */
ldr pc, =HandlerIIC ;/* */
ldr pc, =HandlerSIO ;/* */
ldr pc, =HandlerUTXD0 ;/* */
ldr pc, =HandlerUTXD1 ;/*mGD */
b .
b .
ldr pc, =HandlerRTC ;/*mGKA */
b . ;/* */
b . ;/* */
b . ;/* */
b . ;/* */
b . ;/*mGKA */
b .
b .
ldr pc,=HandlerADC ;/*mGKB
b . ;
b . ;
b . ;
b . ;
b . ;mGKB
b .
b .
ldr pc,=EnterPWDN ;0xe0=EnterPWDN */
ENDIF
HandlerFIQ ;HANDLER HandleFIQ
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleFIQ
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerIRQ ;HANDLER HandleIRQ
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleIRQ
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerUndef ;HANDLER HandleUndef
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleUndef
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerSWI ;HANDLER HandleSWI
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