📄 audio.lst
字号:
C51 COMPILER V7.50 AUDIO 12/14/2005 10:05:36 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE AUDIO
OBJECT MODULE PLACED IN .\OBJ\audio.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE audio.c LARGE OPTIMIZE(9,SIZE) BROWSE PRINT(.\LST\audio.lst) OBJECT(.\OBJ\a
-udio.obj)
line level source
1 /*
2 ********************************************************************************
3 *
4 * Copyright 2002, Vineyard Technologies, Inc.
5 *
6 * Filename : audio.c
7 * Programmer: Steve KyeongHyeon Lee
8 * Created : 2003/08/20
9 * Modified :
10 *
11 * Description :
12 ********************************************************************************
13 */
14
15 #include "types.h"
16
17 /*
18 ###############################################################################
19 File Include Section
20 ###############################################################################
21 */
22 #include "8052reg.h"
23 #include <stdio.h>
24 #include <absacc.h>
25 #include "gio.h"
26 #include "i2c.h"
27 #include "audio.h"
28
29 //==============================================================================
30 // Audio Register in FPGA
31 //==============================================================================
32
33 #define AUDIO_INT_REGISTER XBYTE[0x8000]
34 // bit0: (R) Only used in REC-AUDIO mode, reading this bit will clear audio interrupt at audio FPGA
35 // bit0: (W) Writing 0 will enable audio block in G1P
36 #define AUD_B0_ENALBE 0x00
37
38 #define AUDIO_BUS_REGISTER XBYTE[0x8001]
39 // bit0: (R/W) 0 -> Audio FPGA release IDE bus (automatically by FPGA)
40 // 1 -> Audio FPGA handle IDE bus to read or write
41 // bit1: (W) 0 -> Recoding audio into HDD
42 // 1 -> Decoding audio from HDD
43 #define AUD_B0_AUDIO_IDE 0x01
44
45 #define AUDIO_PLAY_REGISTER XBYTE[0x8002]
46 // bit0: (R/W) 0 -> Audio Recoding Mode Enable
47 // 1 -> Audio Decoding Mode Enable
48 // bit1: (R/W) When READ -> Only in Audio Recording mode, audio interrupt status bit
49 // When WRITE-> Only in Audio Recording mode, toggling this bit make jpeg_header flag in FGPA clear
50 // Actually, this bit is generated by audio FPGA and used by FPGA,
51 // but this bit MUST be cleared by firmware by toggling (1->0).
52 #define AUD_B0_MD_RECORD 0x00
53 #define AUD_B0_MD_PLAY 0x01
54 #define AUD_B1_CLEAR_H 0x02
C51 COMPILER V7.50 AUDIO 12/14/2005 10:05:36 PAGE 2
55
56 #define AUDIO_START_REGISTER XBYTE[0x8003]
57 // bit0: (R/W) 0 -> FPGA audio part reset (every internal variables are cleared
58 // 1 -> start audio recording or playing (make audio FPGA interrupt)
59 // bit1: (R/W) When READ and it is 1 --> audio FPGA is playing audio data and firmware code MUST not activ
-ate VIDEO decoding
60 // 0 --> audio FPGA is not playing any audio data
61 // When WRITE, 1 --> FF mode set for FPGA to skip audio packet
62 // 0 --> Audio FPGA is doing normal audio playing.
63 #define AUD_B0_START 0x01
64 #define AUD_B0_RESET 0x00
65 #define AUD_B1_SKIP 0x02
66 #define AUD_B1_BUSY 0x02
67
68
69 u8 gv_audio_reg_play=0;
70 u8 gv_audio_run=0;
71 u8 gv_audio_IDE_busy=0;
72 u8 gv_audif = FALSE;
73
74 extern void hdd_pre_write(u8 aud_rec_intr);
75
76 void _audioif_clear_IDE_request(void)
77 {
78 1 delay_time(G1REC4KTIME,1);
79 1 hdd_pre_write(1);
80 1 audioif_get_IDE(0x00);
81 1 delay_time(G1REC4KTIME,1);
82 1 // We don't need to release audio IDE because audio part of G1P release IDE automatically
83 1 }
84
85 /*
86 ###############################################################################
87 Reset all of the internal variables in audio FPGA
88 ###############################################################################
89 */
90 void audioif_reset(void)
91 {
92 1 // clear global variables
93 1 gv_audio_reg_play = 0;
94 1 gv_audio_run = 0;
95 1 gv_audio_IDE_busy = 0;
96 1
97 1 if(!gv_audif) return;
98 1
99 1 #ifdef DEBUG_AUDIOIF
printf("\n\raudioif_reset");
#endif
102 1 audio_enable();
103 1
104 1 // check audio record intrrupt is pending
105 1 if(AUDIO_PLAY_REGISTER & 0x02)
106 1 // audio interrupt happen but caller of this function want to stop recording.
107 1 // So we have to give a change to audio block to write audio data onto IDE bus
108 1 {
109 2 _audioif_clear_IDE_request();
110 2 }
111 1
112 1 AUDIO_INT_REGISTER = AUD_B0_ENALBE; // G1P
113 1 AUDIO_START_REGISTER = AUD_B0_RESET;
114 1 delay_time(10,1);
115 1 AUDIO_PLAY_REGISTER = AUD_B0_MD_RECORD;
C51 COMPILER V7.50 AUDIO 12/14/2005 10:05:36 PAGE 3
116 1 dv03_enable();
117 1
118 1 }
119
120 /*
121 ###############################################################################
122 Start audio recording/playing
123 Input: mode
124 0x00 for recording
125 0x01 for playing
126 ###############################################################################
127 */
128 void audioif_start(u8 mode)
129 {
130 1 if(!gv_audif) return;
131 1
132 1 #ifdef DEBUG_AUDIOIF
printf("\n\raudioif_start(%d)", (int)mode);
#endif
135 1
136 1 audio_enable();
137 1 AUDIO_START_REGISTER = AUD_B0_RESET; // Clear Internal Buffer and variable
138 1 delay_time(30,1);
139 1 AUDIO_PLAY_REGISTER = mode;
140 1 AUDIO_START_REGISTER = AUD_B0_START;
141 1 delay_time(30,1);
142 1 dv03_enable();
143 1
144 1 }
145
146
147 /*
148 ###############################################################################
149 Return audio play register value
150 ###############################################################################
151 */
152 u8 audioif_get_regPLAY(void)
153 {
154 1 xdata u8 ret;
155 1
156 1 if(!gv_audif) return 0;
157 1 #ifdef DEBUG_AUDIOIF
printf("\n\raudioif_get_regPLAY");
#endif
160 1 audio_enable();
161 1 ret = AUDIO_PLAY_REGISTER;
162 1 dv03_enable();
163 1 return ret;
164 1 }
165 /*
166 ###############################################################################
167 Clear the internal flag [jpeg_header_flag] in audio FPGA.
168 This function will be called every interrupt.
169 Input:
170 mode : 0x00 in recording mode
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -