bfpga.h

dvr

/*
********************************************************************************
*
* (c) Copyright 2004, Vineyard Technologies, Inc.
*
* Filename : bfgpa.h
* Programmer(s): Steve KyeongHyeon Lee
* Created : 2004/09/30
* Modified :
*
* Description :
********************************************************************************
*/

#include "types.h"

#ifndef __BFPGA_H__
#define __BFPGA_H__

#include <absacc.h>

#define FPGA_REG_BASE		0xC000

#define FPGA_NETBUF_SIZE	2048

#define BFREGOFF_SETUP		0x04
#define BFREGOFF_STATUS		0x05
#define BFREGOFF_ENC_DCTH	0x06
#define BFREGOFF_ENC_ACTH	0x07
#define BFREGOFF_RC_DFR		0x08
#define BFREGOFF_RC_DQL		0x09
#define BFREGOFF_RC_PQL0	0x0A
#define BFREGOFF_RC_PQL1	0x0B
#define BFREGOFF_LAN_DA0	0x0C
#define BFREGOFF_LAN_DA1	0x0D

#define BFREGOFF_TIME_YY	0x0E
#define BFREGOFF_TIME_MM	0x0F
#define BFREGOFF_TIME_DD	0x10
#define BFREGOFF_TIME_HH	0x11
#define BFREGOFF_TIME_NN	0x12
#define BFREGOFF_TIME_SS	0x13


#define BFREG_SETUP		XBYTE[(volatile)0xC004]
//
// bit7: VEN	- video encoding and transmit	- 1:enable
// bit6: VM		- video mode 					- 1:PAL, 0:NTSC
// bit5: VR		- video resolution				- 1:312x224(NTSC)312x272(PAL) 0:624x224(NTSC)624x272(PAL)
// bit4: VBCLR	- internal video buffer clear	- 1:Clear, 0:Normal Operation
// bit3: AEN	- audio encoding and transmit	- 1:enable
// bit2: RCEN	- rate control enable			- 1:enable
// bit1: SRST	- soft reset					- 1:reset
// bit0: START	- start sending 2KB packet 		- 1:start, 0:idle
//
	#define BFS_VEN		0x80
	#define BFS_PAL		0x40
	#define BFS_CIF		0x20
	#define BFS_VBC		0x10
	#define BFS_AEN		0x08
	#define BFS_RCEN	0x04
	#define BFS_RST		0x02
	#define BFS_START	0x01
	
#define BFREG_STATUS	XBYTE[(volatile)0xC005]
//
// bit7: TXINT	- transfer interrupt => MCU's writing this bit will clear interrupt
// bit6: WNINT	- W3100A interrupt   => MCU must write W3100A register to clear interrupt
// bit5: VBOF	- video buffer overflow => MCU's writing this bit will clear this bit
// bit4: ABOF	- audio buffer overflow => MCU's writing this bit will clear this bit
// bit3: N/A
// bit2: N/A
// bit1: N/A
// bit0: READY	- Transfer Ready bit	- 1:Ready, 0:Not Ready
//
	#define TXINT		0x80
	#define WNINT		0x40
	#define VBOF		0x20
	#define ABOF		0x10

#define BFREG_ENC_DCTH	XBYTE[(volatile)0xC006]
#define BFREG_ENC_ACTH	XBYTE[(volatile)0xC007]
#define BFREG_RC_DFR	XBYTE[(volatile)0xC008]	// [RateControl] Default Frame Rate 
#define BFREG_RC_DQL	XBYTE[(volatile)0xC009]
//
// bit7:4 PCFG	- P-frame configuration			- 0:Only I frame, 1:I-P-I-P, 2:I-P-P, 3:I-P-P-P, ...
// bit3:0 DQL	- default video quantize level	- 0:N/A, 1~15:Quantize level
//
#define BFREG_RC_PQL0	XBYTE[(volatile)0xC00A] // [RateControl]
//
// bit7:4 RUQL	- rate up quantize level		- 0:N/A, 1~15:Quantize level
// bit3:0 RDQL	- rate down quantize level		- 0:N/A, 1~15:Quantize level
//
#define BFREG_RC_PQL1	XBYTE[(volatile)0xC00B]
//
// bit7:4 UCQL	- up compensation quantize level	- 0:N/A, 1~15:Quantize level
// bit3:0 DCQL	- down compensation quantize level	- 0:N/A, 1~15:Quantize level
//
#define BFREG_LAN_DA0	XBYTE[(volatile)0xC00C]
#define BFREG_LAN_DA1	XBYTE[(volatile)0xC00D]

#define BFREG_TIME_YY	XBYTE[(volatile)0xC00E]
#define BFREG_TIME_MM	XBYTE[(volatile)0xC00F]
#define BFREG_TIME_DD	XBYTE[(volatile)0xC010]
#define BFREG_TIME_HH	XBYTE[(volatile)0xC011]
#define BFREG_TIME_NN	XBYTE[(volatile)0xC012]
#define BFREG_TIME_SS	XBYTE[(volatile)0xC013]

extern xdata u8 gv_bfpga_move_done;
extern xdata u8 gv_bfpga_move_start;

void bfpga_init(void);
void bfpga_update_regs(u8 off, u8 val);
void bfpga_update_setup(u8 new_setup);
void bfpga_enable_encoding(u8 en);
u8 bfpga_txbuf_ready(void);
void bfpga_txstart(u8 addr_h, u8 addr_l);
#ifdef RESET_VBOF
void bfpga_check_vbof(u8 doitnow);
#endif
void bfpga_update_time(u8* cur_time);
extern xdata u8 vBFREG_SETUP;
extern xdata u8 vBFREG_STATUS;
extern xdata u8 vBFREG_ENC_DCTH;
extern xdata u8 vBFREG_ENC_ACTH;
extern xdata u8 vBFREG_RC_DFR;
extern xdata u8 vBFREG_RC_DQL;
extern xdata u8 vBFREG_RC_PQL0;
extern xdata u8 vBFREG_RC_PQL1;

#endif