📄 invertergrid.mdl
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LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "1.0"
Inductance "1.0"
SetiL0 off
InitialCurrent "0"
Capacitance "125e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Series RLC Branch3"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [447, 225, 473, 250]
Orientation "down"
NamePlacement "alternate"
ShowName off
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "1.0"
Inductance "1.0"
SetiL0 off
InitialCurrent "0"
Capacitance "125e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Universal Bridge"
Ports [1, 0, 0, 0, 0, 3, 2]
Position [225, 117, 270, 193]
Orientation "left"
NamePlacement "alternate"
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Arms "3"
SnubberResistance "1e5"
SnubberCapacitance "inf"
Device "IGBT / Diodes"
Ron "1e-3"
Lon "0"
ForwardVoltages "[ 0 0 ]"
ForwardVoltage "0"
GTOparameters "[ 10e-6 , 20e-6 ]"
IGBTparameters "[ 1e-9, 2e-9 ]"
Measurements "None"
converterType "Rectifier"
}
Block {
BlockType Reference
Name "Vbus"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [115, 165, 135, 200]
Orientation "up"
ShowName off
SourceBlock "powerlib/Electrical\nSources/DC Voltage Source"
SourceType "DC Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "982"
Measurements "None"
}
Block {
BlockType Reference
Name "Vdc "
Tag "PoWeRsYsTeMmEaSuReMeNt"
Ports [0, 1, 0, 0, 0, 2]
Position [55, 138, 80, 162]
Orientation "left"
ForegroundColor "darkGreen"
NamePlacement "alternate"
AttributesFormatString "\\n"
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PhasorSimulation off
OutputType "Magnitude"
PSBequivalent "0"
}
Block {
BlockType SubSystem
Name "control"
Ports [0, 1]
Position [170, 275, 210, 335]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "control"
Location [175, 204, 705, 514]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType From
Name "From1"
Position [25, 119, 85, 141]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Iabc_A"
}
Block {
BlockType From
Name "From2"
Position [25, 74, 85, 96]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Vabc_A"
}
Block {
BlockType From
Name "From3"
Position [25, 209, 85, 231]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Iabc_B"
}
Block {
BlockType From
Name "From4"
Position [25, 164, 85, 186]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Vabc_B"
}
Block {
BlockType From
Name "From5"
Position [25, 254, 85, 276]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Vdc"
}
Block {
BlockType SubSystem
Name "Iabc_A->Iabc_D"
Ports [1, 1]
Position [115, 117, 185, 143]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Iabc_A->Iabc_D"
Location [2, 82, 1014, 721]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Iabc_A"
Position [25, 78, 55, 92]
IconDisplay "Port number"
PortDimensions "3"
}
Block {
BlockType Fcn
Name "Fcn1"
Position [145, 33, 200, 57]
Expr "(u(1)-u(2))/sqrt(3)"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [145, 73, 200, 97]
Expr "(u(2)-u(3))/sqrt(3)"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [145, 113, 200, 137]
Expr "(u(3)-u(1))/sqrt(3)"
}
Block {
BlockType Mux
Name "Mux6"
Ports [3, 1]
Position [225, 25, 230, 145]
ShowName off
Inputs "3"
DisplayOption "bar"
}
Block {
BlockType Outport
Name "Iabc_D"
Position [280, 78, 310, 92]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "Mux6"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "Mux6"
DstPort 2
}
Line {
SrcBlock "Fcn3"
SrcPort 1
DstBlock "Mux6"
DstPort 3
}
Line {
SrcBlock "Iabc_A"
SrcPort 1
Points [35, 0]
Branch {
Points [0, -40]
DstBlock "Fcn1"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "Fcn2"
DstPort 1
}
Branch {
Points [0, 40]
DstBlock "Fcn3"
DstPort 1
}
}
}
Line {
SrcBlock "Mux6"
SrcPort 1
Points [0, 0]
DstBlock "Iabc_D"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "LPF1"
Ports [1, 1]
Position [210, 71, 260, 99]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskPromptString "Control Filter cutoff frequency(Hz):|Sample"
" Time:"
MaskStyleString "edit,edit"
MaskTunableValueString "on,on"
MaskCallbackString "|"
MaskEnableString "on,on"
MaskVisibilityString "on,on"
MaskToolTipString "on,on"
MaskVarAliasString ","
MaskVariables "wcc=@1;Ts=@2;"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "2000|Ts_Power"
MaskTabNameString ","
System {
Name "LPF1"
Location [2, 82, 1014, 721]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Filt in"
Position [20, 103, 50, 117]
IconDisplay "Port number"
}
Block {
BlockType Demux
Name "Demux1"
Ports [1, 3]
Position [75, 44, 80, 176]
BackgroundColor "black"
ShowName off
Outputs "3"
}
Block {
BlockType Reference
Name "LPF1"
Ports [1, 1]
Position [130, 52, 165, 78]
NamePlacement "alternate"
SourceBlock "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\n1st-Order\nFilter"
SourceType "Discrete 1st-Order Filter"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
FilterType "Lowpass"
Tc "1/(2*pi*wcc)"
Ts "Ts"
Initialize "off"
Vac_Init "[0.8 -25 60]"
Vdc_Init "-0.4"
PlotResponse "off"
param1 "[1 500 1]"
}
Block {
BlockType Reference
Name "LPF2"
Ports [1, 1]
Position [130, 97, 165, 123]
NamePlacement "alternate"
SourceBlock "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\n1st-Order\nFilter"
SourceType "Discrete 1st-Order Filter"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
FilterType "Lowpass"
Tc "1/(2*pi*wcc)"
Ts "Ts"
Initialize "off"
Vac_Init "[0.8 -25 60]"
Vdc_Init "-0.4"
PlotResponse "off"
param1 "[1 500 1]"
}
Block {
BlockType Reference
Name "LPF3"
Ports [1, 1]
Position [130, 142, 165, 168]
NamePlacement "alternate"
SourceBlock "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\n1st-Order\nFilter"
SourceType "Discrete 1st-Order Filter"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
FilterType "Lowpass"
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