📄 acdc_test4.mdl
字号:
Location [6, 82, 1018, 713]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Demux
Name "Demux"
Ports [1, 2]
Position [205, 76, 210, 149]
BackgroundColor "black"
ShowName off
Outputs "2"
DisplayOption "bar"
}
Block {
BlockType Demux
Name "Demux1"
Ports [1, 2]
Position [205, 174, 210, 241]
BackgroundColor "black"
ShowName off
Outputs "2"
DisplayOption "bar"
}
Block {
BlockType From
Name "From1"
Position [25, 374, 85, 396]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "vdvq_A"
}
Block {
BlockType From
Name "From5"
Position [20, 29, 80, 51]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "m"
}
Block {
BlockType From
Name "From6"
Position [20, 89, 80, 111]
ShowName off
CloseFcn "tagdialog Close"
GotoTag "IdIq_B"
}
Block {
BlockType From
Name "From7"
Position [20, 114, 80, 136]
ShowName off
CloseFcn "tagdialog Close"
GotoTag "IdIqref"
}
Block {
BlockType From
Name "From8"
Position [25, 424, 85, 446]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "IdIq_A"
}
Block {
BlockType From
Name "From9"
Position [25, 259, 85, 281]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "vdvq_B"
}
Block {
BlockType Gain
Name "Gain"
Position [240, 80, 270, 110]
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [240, 175, 270, 205]
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [235, 420, 265, 450]
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Mux
Name "Mux1"
Ports [2, 1]
Position [110, 85, 115, 140]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux2"
Ports [2, 1]
Position [350, 289, 355, 351]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux3"
Ports [2, 1]
Position [350, 76, 355, 149]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux4"
Ports [2, 1]
Position [350, 171, 355, 244]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux5"
Ports [2, 1]
Position [440, 246, 445, 344]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux7"
Ports [2, 1]
Position [440, 361, 445, 459]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Selector
Name "Selector1"
Ports [1, 1]
Position [520, 258, 545, 292]
ShowName off
Elements "[1 3]"
InputPortWidth "4"
}
Block {
BlockType Selector
Name "Selector2"
Ports [1, 1]
Position [155, 93, 180, 137]
ShowName off
Elements "[1 3]"
InputPortWidth "4"
}
Block {
BlockType Selector
Name "Selector3"
Ports [1, 1]
Position [155, 191, 180, 229]
ShowName off
Elements "[1 3]+1"
InputPortWidth "4"
}
Block {
BlockType Selector
Name "Selector4"
Ports [1, 1]
Position [520, 305, 545, 335]
ShowName off
Elements "[1 3]+1"
InputPortWidth "4"
}
Block {
BlockType Selector
Name "Selector5"
Ports [1, 1]
Position [520, 373, 545, 407]
ShowName off
Elements "[1 3]"
InputPortWidth "4"
}
Block {
BlockType Selector
Name "Selector6"
Ports [1, 1]
Position [520, 420, 545, 450]
ShowName off
Elements "[1 3]+1"
InputPortWidth "4"
}
Block {
BlockType Outport
Name "m"
Position [390, 33, 420, 47]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Id Idref"
Position [390, 108, 420, 122]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Iq Iqref"
Position [385, 203, 415, 217]
Port "3"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "vdId_B"
Position [590, 268, 620, 282]
Port "4"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "vqIq_B"
Position [590, 313, 620, 327]
Port "5"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "vdId_A"
Position [590, 383, 620, 397]
Port "6"
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "vqIq_A"
Position [590, 428, 620, 442]
Port "7"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "From6"
SrcPort 1
DstBlock "Mux1"
DstPort 1
}
Line {
SrcBlock "From7"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Mux1"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "Selector2"
DstPort 1
}
Branch {
Points [0, 95]
DstBlock "Selector3"
DstPort 1
}
}
Line {
SrcBlock "From5"
SrcPort 1
DstBlock "m"
DstPort 1
}
Line {
SrcBlock "Selector2"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Mux3"
SrcPort 1
Points [0, 0]
DstBlock "Id Idref"
DstPort 1
}
Line {
SrcBlock "Selector3"
SrcPort 1
DstBlock "Demux1"
DstPort 1
}
Line {
SrcBlock "Mux4"
SrcPort 1
DstBlock "Iq Iqref"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [40, 0]
Branch {
DstBlock "Mux3"
DstPort 1
}
Branch {
Points [0, 210]
DstBlock "Mux2"
DstPort 1
}
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Mux3"
DstPort 2
}
Line {
SrcBlock "Demux1"
SrcPort 1
DstBlock "Gain1"
DstPort 1
}
Line {
SrcBlock "Demux1"
SrcPort 2
DstBlock "Mux4"
DstPort 2
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Mux5"
SrcPort 1
Points [0, 0; 30, 0]
Branch {
Points [0, -20]
DstBlock "Selector1"
DstPort 1
}
Branch {
Points [0, 25]
DstBlock "Selector4"
DstPort 1
}
}
Line {
SrcBlock "Selector1"
SrcPort 1
Points [0, 0]
DstBlock "vdId_B"
DstPort 1
}
Line {
SrcBlock "Selector4"
SrcPort 1
Points [0, 0]
DstBlock "vqIq_B"
DstPort 1
}
Line {
SrcBlock "Mux2"
SrcPort 1
Points [0, 0]
DstBlock "Mux5"
DstPort 2
}
Line {
SrcBlock "From9"
SrcPort 1
Points [0, 0]
DstBlock "Mux5"
DstPort 1
}
Line {
SrcBlock "Mux7"
SrcPort 1
Points [0, 0; 30, 0]
Branch {
Points [0, 25]
DstBlock "Selector6"
DstPort 1
}
Branch {
Points [0, -20]
DstBlock "Selector5"
DstPort 1
}
}
Line {
SrcBlock "Selector5"
SrcPort 1
DstBlock "vdId_A"
DstPort 1
}
Line {
SrcBlock "Selector6"
SrcPort 1
DstBlock "vqIq_A"
DstPort 1
}
Line {
SrcBlock "From1"
SrcPort 1
DstBlock "Mux7"
DstPort 1
}
Line {
SrcBlock "From8"
SrcPort 1
DstBlock "Gain2"
DstPort 1
}
Line {
SrcBlock "Gain2"
SrcPort 1
DstBlock "Mux7"
DstPort 2
}
Line {
SrcBlock "Gain1"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Mux4"
DstPort 1
}
Branch {
Points [0, 145]
DstBlock "Mux2"
DstPort 2
}
}
}
}
Block {
BlockType Reference
Name "D"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [355, 81, 360, 149]
BackgroundColor "black"
SourceBlock "powerlib/Measurements/Three-Phase\nV-I Measurem"
"ent"
SourceType "Three-Phase VI Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
VoltageMeasurement "phase-to-phase"
SetLabelV on
LabelV "Vabc_D"
Vpu off
CurrentMeasurement "yes"
SetLabelI on
LabelI "Iabc_D"
Ipu off
Pbase "100e6"
Vbase "500e3"
OutputType "Magnitude"
PhasorSimulation off
PSBequivalent "0"
}
Block {
BlockType SubSystem
Name "DC Regulator"
Ports [5, 1]
Position [535, 374, 620, 596]
ForegroundColor "blue"
BackgroundColor "lightBlue"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
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