📄 pmsg_test_w.mdl
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Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType DiscreteIntegrator
IntegratorMethod "Integration: Forward Euler"
gainval "1.0"
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
InitialConditionMode "State and output"
SampleTime "1"
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow off
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
IgnoreLimit off
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType ElementaryMath
Operator "sin"
}
Block {
BlockType From
IconDisplay "Tag"
}
Block {
BlockType Fcn
Expr "sin(u[1])"
SampleTime "-1"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Goto
IconDisplay "Tag"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
Block {
BlockType UnitDelay
X0 "0"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "PMSG_test_w"
Location [2, 82, 997, 717]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "A"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [525, 167, 530, 233]
BackgroundColor "black"
SourceBlock "powerlib/Measurements/Three-Phase\nV-I Measurem"
"ent"
SourceType "Three-Phase VI Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
VoltageMeasurement "phase-to-phase"
SetLabelV on
LabelV "Vabc_A"
Vpu off
CurrentMeasurement "yes"
SetLabelI on
LabelI "Iabc_A"
Ipu off
Pbase "100e6"
Vbase "500e3"
OutputType "Magnitude"
PhasorSimulation off
PSBequivalent "0"
}
Block {
BlockType Reference
Name "B"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [500, 67, 505, 133]
BackgroundColor "black"
SourceBlock "powerlib/Measurements/Three-Phase\nV-I Measurem"
"ent"
SourceType "Three-Phase VI Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
VoltageMeasurement "phase-to-phase"
SetLabelV on
LabelV "Vabc_B"
Vpu off
CurrentMeasurement "yes"
SetLabelI on
LabelI "Iabc_B"
Ipu off
Pbase "100e6"
Vbase "500e3"
OutputType "Magnitude"
PhasorSimulation off
PSBequivalent "0"
}
Block {
BlockType Reference
Name "Cf"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [575, 171, 625, 219]
AttributesFormatString "\\n"
SourceBlock "powerlib/Elements/Three-Phase\nSeries RLC Branc"
"h"
SourceType "Three-Phase Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "A|B|C"
RConnTagsString "A|B|C"
BranchType "R"
Resistance "0.19245"
Inductance "1e-4"
Capacitance "300e-6"
Measurements "None"
}
Block {
BlockType Reference
Name "Cf1"
Ports [0, 0, 0, 0, 0, 3, 3]
Position [550, 71, 600, 119]
AttributesFormatString "\\n"
SourceBlock "powerlib/Elements/Three-Phase\nSeries RLC Branc"
"h"
SourceType "Three-Phase Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "A|B|C"
RConnTagsString "A|B|C"
BranchType "R"
Resistance "0.19245"
Inductance "1e-4"
Capacitance "300e-6"
Measurements "None"
}
Block {
BlockType Reference
Name "Controlled Voltage Source"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [287, 205, 323, 250]
Orientation "up"
ShowName off
SourceBlock "powerlib/Electrical\nSources/Controlled Voltage"
" Source"
SourceType "Controlled Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Initialize on
Source_Type "AC"
Amplitude "0"
Phase "0"
Frequency "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Controlled Voltage Source1"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [327, 220, 363, 265]
Orientation "up"
ShowName off
SourceBlock "powerlib/Electrical\nSources/Controlled Voltage"
" Source"
SourceType "Controlled Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Initialize on
Source_Type "AC"
Amplitude "0"
Phase "0"
Frequency "0"
Measurements "None"
}
Block {
BlockType Reference
Name "Controlled Voltage Source2"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [377, 260, 413, 305]
Orientation "up"
ShowName off
SourceBlock "powerlib/Electrical\nSources/Controlled Voltage"
" Source"
SourceType "Controlled Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Initialize on
Source_Type "AC"
Amplitude "0"
Phase "0"
Frequency "0"
Measurements "None"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 3]
Position [265, 266, 270, 304]
BackgroundColor "black"
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType From
Name "From1"
Position [120, 633, 175, 657]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Iabc_B"
}
Block {
BlockType From
Name "From14"
Position [130, 538, 185, 562]
ForegroundColor "darkGreen"
ShowName off
CloseFcn "tagdialog Close"
GotoTag "Iabc_A"
}
Block {
BlockType From
Name "From15"
Position [60, 474, 120, 496]
ForegroundColor "darkGreen"
ShowName off
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