mips.h.svn-base

PSP用开发必装库GCC4.0.1

   priority than t4.  However, before reload, there is no dependence
   between t1 and t3, and they can often have similar priorities.
   The scheduler will then tend to prefer:

	t1 = a * b
	t3 = e * f
	t2 = t1 + c * d
	t4 = t3 - g * h

   which stops us from making full use of macc/madd-style instructions.
   This sort of situation occurs frequently in Fourier transforms and
   in unrolled loops.

   To counter this, the TUNE_MACC_CHAINS code will reorder the ready
   queue so that chained multiply-add and multiply-subtract instructions
   appear ahead of any other instruction that is likely to clobber lo.
   In the example above, if t2 and t3 become ready at the same time,
   the code ensures that t2 is scheduled first.

   Multiply-accumulate instructions are a bigger win for some targets
   than others, so this macro is defined on an opt-in basis.  */
#define TUNE_MACC_CHAINS	    (TUNE_MIPS5500		\
				     || TUNE_MIPS4120		\
				     || TUNE_MIPS4130)

#define TARGET_OLDABI		    (mips_abi == ABI_32 || mips_abi == ABI_O64)
#define TARGET_NEWABI		    (mips_abi == ABI_N32 || mips_abi == ABI_64)

/* IRIX specific stuff.  */
#define TARGET_IRIX	   0
#define TARGET_IRIX6	   0

/* Define preprocessor macros for the -march and -mtune options.
   PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
   processor.  If INFO's canonical name is "foo", define PREFIX to
   be "foo", and define an additional macro PREFIX_FOO.  */
#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO)			\
  do								\
    {								\
      char *macro, *p;						\
								\
      macro = concat ((PREFIX), "_", (INFO)->name, NULL);	\
      for (p = macro; *p != 0; p++)				\
	*p = TOUPPER (*p);					\
								\
      builtin_define (macro);					\
      builtin_define_with_value ((PREFIX), (INFO)->name, 1);	\
      free (macro);						\
    }								\
  while (0)

/* Target CPU builtins.  */
#define TARGET_CPU_CPP_BUILTINS()				\
  do								\
    {								\
      /* Everyone but IRIX defines this to mips.  */            \
      if (!TARGET_IRIX)                                         \
        builtin_assert ("machine=mips");                        \
                                                                \
      builtin_assert ("cpu=mips");				\
      builtin_define ("__mips__");     				\
      builtin_define ("_mips");					\
								\
      /* We do this here because __mips is defined below	\
	 and so we can't use builtin_define_std.  */		\
      if (!flag_iso)						\
	builtin_define ("mips");				\
								\
      if (TARGET_64BIT)						\
	builtin_define ("__mips64");				\
								\
      if (!TARGET_IRIX)						\
	{							\
	  /* Treat _R3000 and _R4000 like register-size		\
	     defines, which is how they've historically		\
	     been used.  */					\
	  if (TARGET_64BIT)					\
	    {							\
	      builtin_define_std ("R4000");			\
	      builtin_define ("_R4000");			\
	    }							\
	  else							\
	    {							\
	      builtin_define_std ("R3000");			\
	      builtin_define ("_R3000");			\
	    }							\
	}							\
      if (TARGET_FLOAT64)					\
	builtin_define ("__mips_fpr=64");			\
      else							\
	builtin_define ("__mips_fpr=32");			\
								\
      if (TARGET_MIPS16)					\
	builtin_define ("__mips16");				\
								\
      if (TARGET_MIPS3D)					\
	builtin_define ("__mips3d");				\
								\
      MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);	\
      MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);	\
								\
      if (ISA_MIPS1)						\
	{							\
	  builtin_define ("__mips=1");				\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");		\
	}							\
      else if (ISA_MIPS2)					\
	{							\
	  builtin_define ("__mips=2");				\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");		\
	}							\
      else if (ISA_MIPS3)					\
	{							\
	  builtin_define ("__mips=3");				\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");		\
	}							\
      else if (ISA_MIPS4)					\
	{							\
	  builtin_define ("__mips=4");				\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");		\
	}							\
      else if (ISA_MIPS32)					\
	{							\
	  builtin_define ("__mips=32");				\
	  builtin_define ("__mips_isa_rev=1");			\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");	\
	}							\
      else if (ISA_MIPS32R2)					\
	{							\
	  builtin_define ("__mips=32");				\
	  builtin_define ("__mips_isa_rev=2");			\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");	\
	}							\
      else if (ISA_MIPS64)					\
	{							\
	  builtin_define ("__mips=64");				\
	  builtin_define ("__mips_isa_rev=1");			\
	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");	\
	}							\
								\
      if (TARGET_HARD_FLOAT)					\
	builtin_define ("__mips_hard_float");			\
      else if (TARGET_SOFT_FLOAT)				\
	builtin_define ("__mips_soft_float");			\
								\
      if (TARGET_SINGLE_FLOAT)					\
	builtin_define ("__mips_single_float");			\
								\
      if (TARGET_PAIRED_SINGLE_FLOAT)				\
	builtin_define ("__mips_paired_single_float");		\
								\
      if (TARGET_BIG_ENDIAN)					\
	{							\
	  builtin_define_std ("MIPSEB");			\
	  builtin_define ("_MIPSEB");				\
	}							\
      else							\
	{							\
	  builtin_define_std ("MIPSEL");			\
	  builtin_define ("_MIPSEL");				\
	}							\
								\
        /* Macros dependent on the C dialect.  */		\
      if (preprocessing_asm_p ())				\
	{							\
          builtin_define_std ("LANGUAGE_ASSEMBLY");		\
	  builtin_define ("_LANGUAGE_ASSEMBLY");		\
	}							\
      else if (c_dialect_cxx ())				\
        {							\
	  builtin_define ("_LANGUAGE_C_PLUS_PLUS");		\
          builtin_define ("__LANGUAGE_C_PLUS_PLUS");		\
          builtin_define ("__LANGUAGE_C_PLUS_PLUS__");		\
        }							\
      else							\
	{							\
          builtin_define_std ("LANGUAGE_C");			\
	  builtin_define ("_LANGUAGE_C");			\
	}							\
      if (c_dialect_objc ())					\
        {							\
	  builtin_define ("_LANGUAGE_OBJECTIVE_C");		\
          builtin_define ("__LANGUAGE_OBJECTIVE_C");		\
	  /* Bizarre, but needed at least for Irix.  */		\
	  builtin_define_std ("LANGUAGE_C");			\
	  builtin_define ("_LANGUAGE_C");			\
        }							\
								\
      if (mips_abi == ABI_EABI)					\
	builtin_define ("__mips_eabi");				\
								\
} while (0)



/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES							\
{									\
  SUBTARGET_TARGET_SWITCHES                                             \
  {"int64",		  MASK_INT64 | MASK_LONG64,			\
     N_("Use 64-bit int type")},					\
  {"long64",		  MASK_LONG64,					\
     N_("Use 64-bit long type")},					\
  {"long32",		 -(MASK_LONG64 | MASK_INT64),			\
     N_("Use 32-bit long type")},					\
  {"split-addresses",	  MASK_SPLIT_ADDR,				\
     N_("Optimize lui/addiu address loads")},				\
  {"no-split-addresses", -MASK_SPLIT_ADDR,				\
     N_("Don't optimize lui/addiu address loads")},			\
  {"gas",		  0,						\
     N_("Use GNU as (now ignored)")},					\
  {"gpOPT",		  0,						\
     N_("Use GP relative sdata/sbss sections (now ignored)")},		\
  {"gpopt",		  0,						\
     N_("Use GP relative sdata/sbss sections (now ignored)")},		\
  {"no-gpOPT",		  0,					        \
     N_("Don't use GP relative sdata/sbss sections (now ignored)")},	\
  {"no-gpopt",		  0,					        \
     N_("Don't use GP relative sdata/sbss sections (now ignored)")},	\
  {"stats",		  0,						\
     N_("Output compiler statistics (now ignored)")},			\
  {"no-stats",		  0,						\
     N_("Don't output compiler statistics")},				\
  {"memcpy",		  MASK_MEMCPY,					\
     N_("Don't optimize block moves")},					\
  {"no-memcpy",		 -MASK_MEMCPY,					\
     N_("Optimize block moves")},					\
  {"mips-tfile",	  MASK_MIPS_TFILE,				\
     N_("Use mips-tfile asm postpass")},				\
  {"no-mips-tfile",	 -MASK_MIPS_TFILE,				\
     N_("Don't use mips-tfile asm postpass")},				\
  {"soft-float",	  MASK_SOFT_FLOAT,				\
     N_("Use software floating point")},				\
  {"hard-float",	 -MASK_SOFT_FLOAT,				\
     N_("Use hardware floating point")},				\
  {"fp64",		  MASK_FLOAT64,					\
     N_("Use 64-bit FP registers")},					\
  {"fp32",		 -MASK_FLOAT64,					\
     N_("Use 32-bit FP registers")},					\
  {"gp64",		  MASK_64BIT,					\
     N_("Use 64-bit general registers")},				\
  {"gp32",		 -MASK_64BIT,					\
     N_("Use 32-bit general registers")},				\
  {"abicalls",		  MASK_ABICALLS,				\
     N_("Use Irix PIC")},						\
  {"no-abicalls",	 -MASK_ABICALLS,				\
     N_("Don't use Irix PIC")},						\
  {"long-calls",	  MASK_LONG_CALLS,				\
     N_("Use indirect calls")},						\
  {"no-long-calls",	 -MASK_LONG_CALLS,				\
     N_("Don't use indirect calls")},					\
  {"embedded-data",	  MASK_EMBEDDED_DATA,				\
     N_("Use ROM instead of RAM")},					\
  {"no-embedded-data",	 -MASK_EMBEDDED_DATA,				\
     N_("Don't use ROM instead of RAM")},				\
  {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,		\
     N_("Put uninitialized constants in ROM (needs -membedded-data)")},	\
  {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,		\
     N_("Don't put uninitialized constants in ROM")},			\
  {"eb",		  MASK_BIG_ENDIAN,				\
     N_("Use big-endian byte order")},					\
  {"el",		 -MASK_BIG_ENDIAN,				\
     N_("Use little-endian byte order")},				\
  {"single-float",	  MASK_SINGLE_FLOAT,				\
     N_("Use single (32-bit) FP only")},				\
  {"double-float",	 -MASK_SINGLE_FLOAT,				\
     N_("Don't use single (32-bit) FP only")},				\
  {"paired-single",       MASK_PAIRED_SINGLE,				\
     N_("Use paired-single floating point instructions")},		\
  {"no-paired-single",   -MASK_PAIRED_SINGLE,				\
     N_("Use paired-single floating point instructions")},		\
  {"ips3d",               MASK_MIPS3D,					\
     N_("Use MIPS-3D instructions")},					\
  {"no-mips3d",          -MASK_MIPS3D,					\
     N_("Use MIPS-3D instructions")},					\
  {"mad",		  MASK_MAD,					\
     N_("Use multiply accumulate")},					\
  {"no-mad",		 -MASK_MAD,					\
     N_("Don't use multiply accumulate")},				\
  {"no-fused-madd",       MASK_NO_FUSED_MADD,                           \
     N_("Don't generate fused multiply/add instructions")},		\
  {"fused-madd",         -MASK_NO_FUSED_MADD,                           \
     N_("Generate fused multiply/add instructions")},			\
  {"vr4130-align",	  MASK_VR4130_ALIGN,				\
     N_("Perform VR4130-specific alignment optimizations")},		\
  {"no-vr4130-align",	 -MASK_VR4130_ALIGN,				\
     N_("Don't perform VR4130-specific alignment optimizations")},	\
  {"fix4300",             MASK_4300_MUL_FIX,				\
     N_("Work around early 4300 hardware bug")},			\
  {"no-fix4300",         -MASK_4300_MUL_FIX,				\
     N_("Don't work around early 4300 hardware bug")},			\
  {"fix-sb1",             MASK_FIX_SB1,					\
     N_("Work around errata for early SB-1 revision 2 cores")},		\
  {"no-fix-sb1",         -MASK_FIX_SB1,					\
     N_("Don't work around errata for early SB-1 revision 2 cores")},	\
  {"fix-r4000",		  MASK_FIX_R4000,				\
     N_("Work around R4000 errata")},					\
  {"no-fix-r4000",	 -MASK_FIX_R4000,				\
     N_("Don't work around R4000 errata")},				\
  {"fix-r4400",		  MASK_FIX_R4400,				\
     N_("Work around R4400 errata")},					\
  {"no-fix-r4400",	 -MASK_FIX_R4400,				\
     N_("Don't work around R4400 errata")},				\
  {"fix-vr4120",	  MASK_FIX_VR4120,				\
     N_("Work around certain VR4120 errata")},				\
  {"no-fix-vr4120",	 -MASK_FIX_VR4120,				\
     N_("Don't work around certain VR4120 errata")},			\
  {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV,			\
     N_("Trap on integer divide by zero")},				\
  {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV,			\
     N_("Don't trap on integer divide by zero")},			\
  {"divide-traps", -MASK_DIVIDE_BREAKS,					\
     N_("Use trap to check for integer divide by zero")},		\
  {"divide-breaks", MASK_DIVIDE_BREAKS,					\
     N_("Use break to check for integer divide by zero")},		\
  { "branch-likely",      MASK_BRANCHLIKELY,				\
      N_("Use Branch Likely instructions, overriding default for arch")}, \
  { "no-branch-likely",  -MASK_BRANCHLIKELY,				\
      N_("Don't use Branch Likely instructions, overriding default for arch")}, \
  {"explicit-relocs",	  MASK_EXPLICIT_RELOCS,				\
     N_("Use NewABI-style %reloc() assembly operators")},		\
  {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS,				\
     N_("Use assembler macros instead of relocation operators")},	\
  {"ips16",		  MASK_MIPS16,					\
     N_("Generate mips16 code") },					\
  {"no-mips16",		 -MASK_MIPS16,					\
     N_("Generate normal-mode code") },					\
  {"xgot",		  MASK_XGOT,					\
     N_("Lift restrictions on GOT size") },				\
  {"no-xgot",		 -MASK_XGOT,					\
     N_("Do not lift restrictions on GOT size") },			\
  {"fp-exceptions",	  MASK_FP_EXCEPTIONS,				\
     N_("FP exceptions are enabled") },					\