gdb-6.4.patch.svn-base

PSP开发环境(Linux) 包含PSPLINK 请自行选择需要安装的库及源代码

diff -burN gdb-6.4/bfd/archures.c gdb-psp/bfd/archures.c
--- gdb-6.4/bfd/archures.c	2005-10-25 18:40:09.000000000 +0100
+++ gdb-psp/bfd/archures.c	2007-02-08 20:06:04.000000000 +0000
@@ -154,6 +154,7 @@
 .#define bfd_mach_mips16		16
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_allegrex         10111431 {* octal 'AL', 31 *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
diff -burN gdb-6.4/bfd/bfd-in2.h gdb-psp/bfd/bfd-in2.h
--- gdb-6.4/bfd/bfd-in2.h	2005-10-25 18:40:09.000000000 +0100
+++ gdb-psp/bfd/bfd-in2.h	2007-02-08 20:06:04.000000000 +0000
@@ -1742,6 +1742,7 @@
 #define bfd_mach_mips16                16
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_allegrex         10111431 /* octal 'AL', 31 */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
diff -burN gdb-6.4/bfd/cpu-mips.c gdb-psp/bfd/cpu-mips.c
--- gdb-6.4/bfd/cpu-mips.c	2005-05-04 16:53:06.000000000 +0100
+++ gdb-psp/bfd/cpu-mips.c	2007-02-08 20:06:04.000000000 +0000
@@ -86,6 +86,7 @@
   I_mipsisa64,
   I_mipsisa64r2,
   I_sb1,
+  I_allegrex,
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -118,7 +119,8 @@
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
-  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
+  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
+  N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff -burN gdb-6.4/bfd/elfxx-mips.c gdb-psp/bfd/elfxx-mips.c
--- gdb-6.4/bfd/elfxx-mips.c	2005-10-25 17:19:08.000000000 +0100
+++ gdb-psp/bfd/elfxx-mips.c	2007-02-08 20:06:04.000000000 +0000
@@ -4666,6 +4666,9 @@
     case E_MIPS_MACH_SB1:
       return bfd_mach_mips_sb1;
 
+    case E_MIPS_MACH_ALLEGREX:
+      return bfd_mach_mips_allegrex;
+
     default:
       switch (flags & EF_MIPS_ARCH)
 	{
@@ -7950,6 +7953,10 @@
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
       break;
 
+    case bfd_mach_mips_allegrex:
+      val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
+      break;
+
     case bfd_mach_mipsisa32:
       val = E_MIPS_ARCH_32;
       break;
@@ -9648,6 +9655,7 @@
   /* MIPS II extensions.  */
   { bfd_mach_mips4000, bfd_mach_mips6000 },
   { bfd_mach_mipsisa32, bfd_mach_mips6000 },
+  { bfd_mach_mips_allegrex, bfd_mach_mips6000 },
 
   /* MIPS I extensions.  */
   { bfd_mach_mips6000, bfd_mach_mips3000 },
diff -burN gdb-6.4/config.sub gdb-psp/config.sub
--- gdb-6.4/config.sub	2005-07-14 02:24:56.000000000 +0100
+++ gdb-psp/config.sub	2007-02-08 20:06:04.000000000 +0000
@@ -256,6 +256,7 @@
 	| mipsisa64sb1 | mipsisa64sb1el \
 	| mipsisa64sr71k | mipsisa64sr71kel \
 	| mipstx39 | mipstx39el \
+	| mipsallegrex | mipsallegrexel \
 	| mn10200 | mn10300 \
 	| ms1 \
 	| msp430 \
@@ -335,6 +336,7 @@
 	| mipsisa64sb1-* | mipsisa64sb1el-* \
 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
 	| mipstx39-* | mipstx39el-* \
+	| mipsallegrex-* | mipsallegrexel-* \
 	| mmix-* \
 	| ms1-* \
 	| msp430-* \
@@ -678,6 +680,10 @@
 		basic_machine=m68k-atari
 		os=-mint
 		;;
+	psp)
+		basic_machine=mipsallegrexel-psp
+		os=-elf
+		;;
 	mips3*-*)
 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
 		;;
diff -burN gdb-6.4/gdb/remote.c gdb-psp/gdb/remote.c
--- gdb-6.4/gdb/remote.c	2005-07-20 03:56:43.000000000 +0100
+++ gdb-psp/gdb/remote.c	2007-02-08 20:06:12.000000000 +0000
@@ -1953,6 +1953,7 @@
   int lose;
   CORE_ADDR text_addr, data_addr, bss_addr;
   struct section_offsets *offs;
+  int i;
 
   putpkt ("qOffsets");
 
@@ -2014,6 +2015,13 @@
   memcpy (offs, symfile_objfile->section_offsets,
 	  SIZEOF_N_SECTION_OFFSETS (symfile_objfile->num_sections));
 
+  /* GDB is stupid, lets fix up all sections to the same address not just a few :P */
+
+  for(i = 0; i < symfile_objfile->num_sections; i++)
+  {
+	  offs->offsets[i] = text_addr;
+  }
+#if 0
   offs->offsets[SECT_OFF_TEXT (symfile_objfile)] = text_addr;
 
   /* This is a temporary kludge to force data and bss to use the same offsets
@@ -2022,6 +2030,7 @@
 
   offs->offsets[SECT_OFF_DATA (symfile_objfile)] = data_addr;
   offs->offsets[SECT_OFF_BSS (symfile_objfile)] = data_addr;
+#endif
 
   objfile_relocate (symfile_objfile, offs);
 }
diff -burN gdb-6.4/include/bin-bugs.h gdb-psp/include/bin-bugs.h
--- gdb-6.4/include/bin-bugs.h	2004-07-23 16:40:19.000000000 +0100
+++ gdb-psp/include/bin-bugs.h	2007-02-08 20:06:04.000000000 +0000
@@ -1,3 +1,3 @@
 #ifndef REPORT_BUGS_TO
-#define REPORT_BUGS_TO	"<URL:http://www.sourceware.org/bugzilla/>"
+#define REPORT_BUGS_TO	"<URL:http://wiki.pspdev.org/psp:toolchain#bugs>"
 #endif
diff -burN gdb-6.4/include/elf/common.h gdb-psp/include/elf/common.h
--- gdb-6.4/include/elf/common.h	2005-09-30 16:12:52.000000000 +0100
+++ gdb-psp/include/elf/common.h	2007-02-08 20:06:04.000000000 +0000
@@ -93,6 +93,7 @@
 #define ET_HIOS		0xFEFF	/* Operating system-specific */
 #define ET_LOPROC	0xFF00	/* Processor-specific */
 #define ET_HIPROC	0xFFFF	/* Processor-specific */
+#define ET_PSPEXEC	0xFFA0	/* Sony PSP executable file */
 
 /* Values for e_machine, which identifies the architecture.  These numbers
    are officially assigned by [e-mail].  See below for a list of
diff -burN gdb-6.4/include/elf/mips.h gdb-psp/include/elf/mips.h
--- gdb-6.4/include/elf/mips.h	2005-05-10 11:21:10.000000000 +0100
+++ gdb-psp/include/elf/mips.h	2007-02-08 20:06:04.000000000 +0000
@@ -212,6 +212,7 @@
 #define E_MIPS_MACH_5400	0x00910000
 #define E_MIPS_MACH_5500	0x00980000
 #define E_MIPS_MACH_9000	0x00990000
+#define E_MIPS_MACH_ALLEGREX	0x00A20000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff -burN gdb-6.4/include/opcode/mips.h gdb-psp/include/opcode/mips.h
--- gdb-6.4/include/opcode/mips.h	2005-09-06 19:42:58.000000000 +0100
+++ gdb-psp/include/opcode/mips.h	2007-02-08 20:06:04.000000000 +0000
@@ -203,6 +203,83 @@
 #define MDMX_FMTSEL_VEC_QH	0x15
 #define MDMX_FMTSEL_VEC_OB	0x16
 
+#define OP_SH_VFPU_DELTA	0
+#define OP_MASK_VFPU_DELTA	0xfffc
+#define OP_SH_VFPU_IMM3		16
+#define OP_MASK_VFPU_IMM3	0x7
+#define OP_SH_VFPU_IMM5		16
+#define OP_MASK_VFPU_IMM5	0x1f
+#define OP_SH_VFPU_IMM8		16
+#define OP_MASK_VFPU_IMM8	0xff
+#define OP_SH_VFPU_CC		18	/* Condition code. */
+#define OP_MASK_VFPU_CC		0x7
+#define OP_SH_VFPU_CONST	16
+#define OP_MASK_VFPU_CONST	0x1f
+#define OP_SH_VFPU_COND		0	/* Conditional compare. */
+#define OP_MASK_VFPU_COND	0xf
+#define OP_SH_VFPU_VMTVC	0
+#define OP_MASK_VFPU_VMTVC	0xff
+#define OP_SH_VFPU_VMFVC	8
+#define OP_MASK_VFPU_VMFVC	0xff
+#define OP_SH_VFPU_RWB		1
+#define OP_MASK_VFPU_RWB	0x1
+#define OP_SH_VFPU_ROT		16	/* Rotators used in vrot. */
+#define OP_MASK_VFPU_ROT	0x1f
+#define OP_SH_VFPU_FLOAT16	0
+#define OP_MASK_VFPU_FLOAT16	0xffff
+
+/* VFPU registers. */
+#define OP_SH_VFPU_VD		0
+#define OP_MASK_VFPU_VD		0x7f
+#define OP_SH_VFPU_VS		8
+#define OP_MASK_VFPU_VS		0x7f
+#define OP_SH_VFPU_VT		16
+#define OP_MASK_VFPU_VT		0x7f
+#define OP_SH_VFPU_VT_LO	16	/* Bits 0-4 of vt. */
+#define OP_MASK_VFPU_VT_LO	0x1f
+#define OP_SH_VFPU_VT_HI	5	/* Right-shifted. */
+#define OP_MASK_VFPU_VT_HI1	0x1	/* Bit 5 of vt. */
+#define OP_MASK_VFPU_VT_HI2	0x3	/* Bits 5-6 of vt. */
+/* Special handling of vs in vmmul instructions. */
+#define VFPU_OP_VT_VS_VD	0xff800000
+#define VFPU_OPCODE_VMMUL	0xf0000000
+
+/* VFPU prefix instruction operands.  The *_SH_* values really specify where
+   the bitfield begins, as VFPU prefix instructions have four operands
+   encoded within the immediate field. */
+#define VFPU_SH_PFX_NEG		16
+#define VFPU_MASK_PFX_NEG	0x1	/* Negation. */
+#define VFPU_SH_PFX_CST		12
+#define VFPU_MASK_PFX_CST	0x1	/* Constant. */
+#define VFPU_SH_PFX_ABS_CSTHI	8
+#define VFPU_MASK_PFX_ABS_CSTHI	0x1	/* Abs/Constant (bit 2). */
+#define VFPU_MASK_PFX_SWZ_CSTLO	0x3	/* Swizzle/Constant (bits 0-1). */
+#define VFPU_SH_PFX_MASK	8
+#define VFPU_MASK_PFX_MASK	0x1	/* Mask. */
+#define VFPU_MASK_PFX_SAT	0x3	/* Saturation. */
+
+/* Special handling of the vrot instructions. */
+#define VFPU_MASK_OP_SIZE	0x8080	/* Masks the operand size (pair, triple, quad). */
+#define VFPU_OP_SIZE_PAIR	0x80
+#define VFPU_OP_SIZE_TRIPLE	0x8000
+#define VFPU_OP_SIZE_QUAD	0x8080
+/* Note that these are within the rotators field, and not the full opcode. */
+#define VFPU_SH_ROT_HI		2
+#define VFPU_MASK_ROT_HI	0x3
+#define VFPU_SH_ROT_LO		0
+#define VFPU_MASK_ROT_LO	0x3
+#define VFPU_SH_ROT_NEG		4	/* Negation. */
+#define VFPU_MASK_ROT_NEG	0x1
+
+/* VFPU 16-bit floating-point format. */
+#define VFPU_FLOAT16_EXP_MAX	0x1f
+#define VFPU_SH_FLOAT16_SIGN	15
+#define VFPU_MASK_FLOAT16_SIGN	0x1
+#define VFPU_SH_FLOAT16_EXP	10
+#define VFPU_MASK_FLOAT16_EXP	0x1f
+#define VFPU_SH_FLOAT16_FRAC	0
+#define VFPU_MASK_FLOAT16_FRAC	0x3ff
+
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
@@ -290,6 +367,29 @@
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 < (pos+size) <= 64.
 
+   Sony Allegrex VFPU instructions:
+   "?o"
+   "?0" - "?3"
+   "?4" - "?7"
+   "?a"
+   "?b"
+   "?c"
+   "?e"
+   "?f"
+   "?i"
+   "?q"
+   "?r"
+   "?u"
+   "?w"
+   "?d"
+   "?m"
+   "?n"
+   "?s"
+   "?t"
+   "?v"
+   "?x"
+   "?z"
+
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
@@ -500,6 +600,8 @@
 #define INSN_5400		  0x01000000
 /* NEC VR5500 instruction.  */