📄 binutils-2.16.1.patch.svn-base
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+ cst = 3;+ else if (s[0] == '3')+ cst = 5;+ else if (s[0] == '4')+ cst = 6;+ else if (s[0] == '6')+ cst = 7;+ else+ pfx_err = 1;+ }+ else+ {+ cst = 1;+ }+ }+ else if (s[0] == '2')+ cst = 2;+ else if (s[0] == '3')+ cst = 4;+ else+ pfx_err = 1;++ pfx_abs = (cst >> 2) & 0x1;+ pfx_swz = (cst >> 0) & 0x3;+ s++;+ }+ else+ { // variable+ + if (s[0] == '|')+ { // abs+ pfx_abs = 1;+ s++;+ }+ + if ((s[0] == 'X') || (s[0] == 'x'))+ {+ pfx_swz = 0;+ s++;+ }+ else if ((s[0] == 'Y') || (s[0] == 'y'))+ {+ pfx_swz = 1;+ s++;+ }+ else if ((s[0] == 'Z') || (s[0] == 'z'))+ {+ pfx_swz = 2;+ s++;+ }+ else if ((s[0] == 'W') || (s[0] == 'w'))+ {+ pfx_swz = 3;+ s++;+ }+ else if ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])+ || (s[0] == '|'))+ {+ pfx_swz = *args - '0';+ }+ else+ pfx_err = 1;++ if (pfx_err == 0)+ {+ if (s[0] == '|')+ {+ s++;+ if (pfx_abs == 0)+ pfx_err = 1;+ }+ else+ {+ if (pfx_abs == 1)+ pfx_err = 1;+ }+ }+ }++ if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))+ pfx_err = 1;++ if (pfx_err)+ as_bad (_("Invalid prefix format (%s)"), pfx_str);++ shift = *args - '0';++ operand = (pfx_neg << (VF_SH_PFX_NEG + shift))+ | (pfx_cst << (VF_SH_PFX_CST + shift))+ | (pfx_abs << (VF_SH_PFX_ABS + shift))+ | (pfx_swz << (VF_SH_PFX_SWZ + shift * 2));++ ip->insn_opcode |= operand;+ continue;+ }++ case '4': /* destination prefix code (X) */+ case '5': /* destination prefix code (Y) */+ case '6': /* destination prefix code (Z) */+ case '7': /* destination prefix code (W) */+ {+ int operand;+ int shift;+ static const char order[] = "xyzwXYZW";++ int pfx_msk = 0;+ int pfx_sat = 0;+ char *pfx_str = s;++ if (s[0] == '[')+ s++;+ if (s[0] == '-') /* -1:1, skip the minus symbol */+ s++;++ if ((s[0] == 'm') || (s[0] == 'M'))+ {+ pfx_msk = 1;+ s++;+ }+ else if (s[0] == '0') /* 0:1 */+ {+ pfx_sat = 1;+ s++;+ }+ else if (s[0] == '1') /* -1:1 or -1:+1 */+ {+ pfx_sat = 3;+ s++;+ }+ else if ((s[0] == order[(*args) - '4'])+ || (s[0] == order[(*args) - '4' + 4]))+ {+ pfx_sat = 0;+ s++;+ }++ if (s[0] == ':') /* skip the :1 or :+1 part of the expression */+ {+ s++;+ if (s[0] == '+')+ s++;+ if (s[0] == '1')+ s++;+ }+ if (s[0] == ']')+ s++;++ if (! ((s[0] == ',') || IS_SPACE_OR_NUL (s[0])))+ as_bad (_("Invalid prefix format (%s)"), pfx_str);++ shift = *args - '4';+ operand = (pfx_msk << (VF_SH_PFX_MSK + shift))+ | (pfx_sat << (VF_SH_PFX_SAT + shift * 2));++ ip->insn_opcode |= operand;+ continue;+ }+ }+ break;++ case 'b': /* base register */+ case 'd': /* destination register */+ case 's': /* source register */+ case 't': /* target register */+ case 'r': /* both target and source */+ case 'v': /* both dest and source */+ case 'w': /* both dest and target */+ case 'E': /* coprocessor target register */+ case 'G': /* coprocessor destination register */+ case 'K': /* 'rdhwr' destination register */+ case 'x': /* ignore register name */+ case 'z': /* must be zero register */+ case 'U': /* destination register (clo/clz). */+ s_reset = s;+ if (s[0] == '$')+ {++ if (ISDIGIT (s[1]))+ {+ ++s; regno = 0; do {@@ -8273,30 +9967,27 @@ goto notreg; else {- if (s[1] == 'r' && s[2] == 'a')+ const char regName[32][5] = {- s += 3;- regno = RA;- }- else if (s[1] == 'f' && s[2] == 'p')+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",+ "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"+ };+ int i;++ for(i = 0; i < 32; i++) {- s += 3;- regno = FP;- }- else if (s[1] == 's' && s[2] == 'p')+ if(strncmp(&s[1], regName[i], strlen(regName[i])) == 0) {- s += 3;- regno = SP;+ break; }- else if (s[1] == 'g' && s[2] == 'p')- {- s += 3;- regno = GP; }- else if (s[1] == 'a' && s[2] == 't')++ if(i < 32) {- s += 3;- regno = AT;+ s += strlen(regName[i]) + 1;+ regno = i; } else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') {@@ -8485,6 +10176,7 @@ if ((regno & 1) != 0 && HAVE_32BIT_FPRS+ && ! CPU_IS_ALLEGREX (mips_opts.arch) && ! (strcmp (str, "mtc1") == 0 || strcmp (str, "mfc1") == 0 || strcmp (str, "lwc1") == 0@@ -13743,6 +15435,8 @@ /* MIPS II */ { "r6000", 0, ISA_MIPS2, CPU_R6000 },+ /* Sony PSP "Allegrex" CPU core */+ { "allegrex", 0, ISA_MIPS2, CPU_ALLEGREX }, /* MIPS III */ { "r4000", 0, ISA_MIPS3, CPU_R4000 },diff -burN binutils-2.16.1/gas/configure binutils-psp/gas/configure--- binutils-2.16.1/gas/configure 2005-03-01 00:43:51.000000000 +0000+++ binutils-psp/gas/configure 2006-05-09 02:55:36.000000000 +0100@@ -4537,6 +4537,9 @@ mips64vr | mips64vrel) mips_cpu=vr4100 ;;+ mipsallegrex | mipsallegrexel)+ mips_cpu=allegrex+ ;; mipsisa32r2* | mipsisa64r2*) mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` ;;diff -burN binutils-2.16.1/gas/configure.in binutils-psp/gas/configure.in--- binutils-2.16.1/gas/configure.in 2005-03-01 00:43:57.000000000 +0000+++ binutils-psp/gas/configure.in 2006-05-09 02:55:36.000000000 +0100@@ -222,6 +222,9 @@ mips64vr | mips64vrel) mips_cpu=vr4100 ;;+ mipsallegrex | mipsallegrexel)+ mips_cpu=allegrex+ ;; mipsisa32r2* | mipsisa64r2*) changequote(,)dnl mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'`diff -burN binutils-2.16.1/gas/testsuite/gas/mips/mips.exp binutils-psp/gas/testsuite/gas/mips/mips.exp--- binutils-2.16.1/gas/testsuite/gas/mips/mips.exp 2005-04-19 18:09:45.000000000 +0100+++ binutils-psp/gas/testsuite/gas/mips/mips.exp 2006-05-09 02:55:36.000000000 +0100@@ -382,6 +382,9 @@ mips_arch_create sb1 64 mips64 { mips3d } \ { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \ { mipsisa64sb1-*-* mipsisa64sb1el-*-* }+mips_arch_create allegrex 32 mips2 { ror } \+ { -march=allegrex -mtune=allegrex } { -mmips:allegrex } \+ { mipsallegrex-*-* mipsallegrexel-*-* } #diff -burN binutils-2.16.1/include/bin-bugs.h binutils-psp/include/bin-bugs.h--- binutils-2.16.1/include/bin-bugs.h 2004-07-23 16:40:19.000000000 +0100+++ binutils-psp/include/bin-bugs.h 2006-05-09 02:55:36.000000000 +0100@@ -1,3 +1,3 @@ #ifndef REPORT_BUGS_TO-#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>"+#define REPORT_BUGS_TO "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>" #endifdiff -burN binutils-2.16.1/include/elf/common.h binutils-psp/include/elf/common.h--- binutils-2.16.1/include/elf/common.h 2004-10-08 14:55:08.000000000 +0100+++ binutils-psp/include/elf/common.h 2006-05-09 02:55:36.000000000 +0100@@ -93,6 +93,7 @@ #define ET_HIOS 0xFEFF /* Operating system-specific */ #define ET_LOPROC 0xFF00 /* Processor-specific */ #define ET_HIPROC 0xFFFF /* Processor-specific */+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */ /* Values for e_machine, which identifies the architecture. These numbers are officially assigned by registry@caldera.com. See below for a list ofdiff -burN binutils-2.16.1/include/elf/mips.h binutils-psp/include/elf/mips.h--- binutils-2.16.1/include/elf/mips.h 2005-03-03 11:58:06.000000000 +0000+++ binutils-psp/include/elf/mips.h 2006-05-09 02:55:36.000000000 +0100@@ -212,6 +212,7 @@ #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5500 0x00980000 #define E_MIPS_MACH_9000 0x00990000+#define E_MIPS_MACH_ALLEGREX 0x00A20000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of thesediff -burN binutils-2.16.1/include/opcode/mips.h binutils-psp/include/opcode/mips.h--- binutils-2.16.1/include/opcode/mips.h 2005-03-03 11:58:10.000000000 +0000+++ binutils-psp/include/opcode/mips.h 2006-05-09 02:55:36.000000000 +0100@@ -171,6 +171,228 @@ #define MDMX_FMTSEL_VEC_QH 0x15 #define MDMX_FMTSEL_VEC_OB 0x16 +#include "vfpu.h"++#define VF_MASK_VT 0x7f+#define VF_SH_VT 16+#define VF_MASK_VS 0x7f+#define VF_SH_VS 8+#define VF_MASK_VD 0x7f+#define VF_SH_VD 0+#define VF_MASK_VML 0x1f+#define VF_SH_VML 16+#define VF_MASK_VMH 0x3+#define VF_SH_VMH 0+#define VF_MASK_VNL 0x1f+#define VF_SH_VNL 16+#define VF_MASK_VNH 0x1+#define VF_SH_VNH 0+#define VF_MASK_OFFSET 0x3fff+#define VF_SH_OFFSET 2+#define VF_MASK_CC 0xf+#define VF_SH_CC 0+#define VF_MASK_CONST 0x1f+#define VF_SH_CONST 16+#define VF_MASK_SCALE 0x1f+#define VF_SH_SCALE 16+#define VF_MASK_BCOND 0x7+#define VF_SH_BCOND 18+#define VF_MASK_MCOND 0x7+#define VF_SH_MCOND 16+#define VF_MASK_VCD 0xff+#define VF_SH_VCD 0+#define VF_MASK_VCS 0xff+#define VF_SH_VCS 8+#define VF_MASK_ROT 0x1f+#define VF_SH_ROT 16+#define VF_MASK_WRAP 0xff+#define VF_SH_WRAP 16+#define VF_MASK_TSIGN 0x1+#define VF_SH_TSIGN 5+#define VF_MASK_BMCOND 0x1f+#define VF_SH_BMCOND 0+#define VF_MASK_HFLOAT 0xffff+#define VF_SH_HFLOAT 0+#define VF_MASK_PFX 0xffffff+#define VF_SH_PFX 0+#define VF_MASK_RWB 0x1+#define VF_SH_RWB 1++#define VF_MASK_PFX_SWZ 0x3+#define VF_SH_PFX_SWZ 0+#define VF_MASK_PFX_ABS 0x1+#define VF_SH_PFX_ABS 8+#define VF_MASK_PFX_CST 0x1+#define VF_SH_PFX_CST 12+#define VF_MASK_PFX_NEG 0x1+#define VF_SH_PFX_NEG 16+#define VF_MASK_PFX_SAT 0x3+#define VF_SH_PFX_SAT 0+#define VF_MASK_PFX_MSK 0x1+#define VF_SH_PFX_MSK 8++#define VF_MASK_ROT_COS 0x3+#define VF_SH_ROT_COS 0+#define VF_MASK_ROT_SIN 0x3+#define VF_SH_ROT_SIN 2+#define VF_MASK_ROT_NEG 0x1+#define VF_SH_ROT_NEG 4++#define VF_MASK_MR_MTX 0x7+#define VF_SH_MR_MTX 2+#define VF_MASK_MR_IDX 0x3+#define VF_SH_MR_IDX 0+#define VF_MASK_MR_FSL 0x3+#define VF_SH_MR_FSL 5+#define VF_MASK_MR_RXC 0x1+#define VF_SH_MR_RXC 5+#define VF_MASK_MR_VFSL 0x1+#define VF_SH_MR_VFSL 6++#define VF_MAX_MR_MTX 7+#define VF_MAX_MR_IDX 3+#define VF_MAX_MR_FSL 3+#define VF_MAX_MR_VIDX 1+#define VF_MAX_MR_VFSL 1++#define VF_MIN_MR 0+#define VF_MAX_MR 127+#define VF_MIN_CR 128+#define VF_MAX_CR 255+#define VF_MIN_VCR 128+#define VF_MAX_VCR 143+#define VF_MIN_CC 0+#define VF_MAX_CC 15+#define VF_MIN_CONST 1+#define VF_MAX_CONST 19+#define VF_MIN_SCALE 0+#define VF_MAX_SCALE 31+#define VF_MIN_BCOND 0+#define VF_MAX_BCOND 5+#define VF_MIN_MCOND 0+#define VF_MAX_MCOND 6+#define VF_MIN_WRAP 0+#define VF_MAX_WRAP 255+#define VF_MIN_ROT 0+#define VF_MAX_ROT 31+#define VF_MIN_TSIGN 0+#define VF_MAX_TSIGN 1+#define VF_MIN_BMCOND 0+#define VF_MAX_BMCOND 31+#define VF_MIN_HFLOAT 0+#define VF_MAX_HFLOAT 0xffff++#define VF_MASK_F32_SIGN 0x1+#define VF_SH_F32_SIGN 31+#define VF_MASK_F32_EXP 0xff+#define VF_SH_F32_EXP 23+#define VF_MASK_F32_FRA 0x7fffff+#define VF_SH_F32_FRA 0+#define VF_MASK_F16_SIGN 0x1+#define VF_SH_F16_SIGN 15+#define VF_MASK_F16_EXP 0x1f+#define VF_SH_F16_EXP 10+#define VF_MASK_F16_FRA 0x3ff+#define VF_SH_F16_FRA 0++#define VF_MIN_F32_EXP 0+#define VF_MAX_F32_EXP 255+#define VF_BIAS_F32_EXP 127+#define VF_MIN_F16_EXP 0+#define VF_MAX_F16_EXP 31+#define VF_BIAS_F16_EXP 15++#define OP_SH_VFPU_DELTA 0+#define OP_MASK_VFPU_DELTA 0xfffc+#define OP_SH_VFPU_IMM3 16+#define OP_MASK_VFPU_IMM3 0x7+#define OP_SH_VFPU_IMM5 16+#define OP_MASK_VFPU_IMM5 0x1f+#define OP_SH_VFPU_IMM8 16+#define OP_MASK_VFPU_IMM8 0xff+#define OP_SH_VFPU_CC 18 /* Condition code. */+#define OP_MASK_VFPU_CC 0x7+#define OP_SH_VFPU_CONST 16+#define OP_MASK_VFPU_CONST 0x1f+#define OP_SH_VFPU_COND 0 /* Conditional compare. */+#define OP_MASK_VFPU_COND 0xf+#define OP_SH_VFPU_VMTVC 0+#define OP_MASK_VFPU_VMTVC 0xff+#define OP_SH_VFPU_VMFVC 8+#def⌨️ 快捷键说明
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