binutils-2.16.1.patch.svn-base

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 	  || mask == M_L_DAB
 	  || mask == M_S_DAB)
 	fmt = "T,o(b)";
+      else if (mask == M_LV_S_AB
+	       || mask == M_SV_S_AB)
+	{
+	  fmt = "?m0x,?o(b)";
+	  treg = vmreg;
+	}
+      else if (mask == M_LV_Q_AB
+	       || mask == M_SV_Q_AB
+	       || mask == M_LVL_Q_AB
+	       || mask == M_LVR_Q_AB
+	       || mask == M_SVL_Q_AB
+	       || mask == M_SVR_Q_AB)
+	{
+	  fmt = "?n3x,?o(b)";
+	  treg = vmreg;
+	}
       else if (coproc)
 	fmt = "E,o(b)";
       else
@@ -6150,6 +6364,138 @@
 	  break;
 	}
 
+    case M_LVI_S_SS:
+    case M_LVI_P_SS:
+    case M_LVI_T_SS:
+    case M_LVI_Q_SS:
+      {
+	int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
+	int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
+	int fsl = 0;
+	int rxc = 0;
+	int vtreg_s = 0;
+	int vnum = 0;
+	int vat = 0;
+	int i;
+
+	switch (mask)
+	  {
+	  case M_LVI_S_SS:
+	    vnum = 1;
+	    fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
+	    rxc = 0;
+	    break;
+	  case M_LVI_P_SS:
+	    vnum = 2;
+	    fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1;
+	    rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
+	    break;
+	  case M_LVI_T_SS:
+	    vnum = 3;
+	    fsl = (vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL;
+	    rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
+	    break;
+	  case M_LVI_Q_SS:
+	    vnum = 4;
+	    fsl = 0;
+	    rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
+	    break;
+	  }
+	if (rxc)
+	  vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL)
+		  | (fsl << VF_SH_MR_IDX);
+	else
+	  vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX)
+		  | (fsl << VF_SH_MR_FSL);
+
+	for (i = 0; i < vnum; i++) {
+	  imm_expr = vimm_expr[i];
+	  offset_expr = voffset_expr[i];
+
+	  if (imm_expr.X_op == O_constant)
+	    {
+	      load_register (AT, &imm_expr, 0);
+	      macro_build ((expressionS *) NULL,
+			   "mtv", "t,?d0z", AT, vtreg_s);
+	      vat = 1;
+	    }
+	  else
+	    {
+	      assert (offset_expr.X_op == O_symbol
+		      && strcmp (segment_name (S_GET_SEGMENT
+					       (offset_expr.X_add_symbol)),
+				 ".lit4") == 0
+		      && offset_expr.X_add_number == 0);
+	      macro_build (&offset_expr,
+			   "lv.s", "?m0x,?o(b)", vtreg_s,
+			   (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
+	    }
+
+	  if (rxc)
+	    vtreg_s += (1 << VF_SH_MR_IDX);
+	  else
+	    vtreg_s += (1 << VF_SH_MR_FSL);
+	}
+
+	if (vat)
+	  break;
+	else
+	  return;
+      }
+
+    case M_LVHI_S_SS:
+    case M_LVHI_P_SS:
+      {
+	int mtx = (vtreg >> VF_SH_MR_MTX) & VF_MASK_MR_MTX;
+	int idx = (vtreg >> VF_SH_MR_IDX) & VF_MASK_MR_IDX;
+	int fsl = 0;
+	int rxc = 0;
+	int vtreg_s = 0;
+	int vnum = 0;
+	int i;
+	unsigned int f16v;
+	char f16v_str[16];
+
+	switch (mask)
+	  {
+	  case M_LVHI_S_SS:
+	    vnum = 2;
+	    fsl = (vtreg >> VF_SH_MR_FSL) & VF_MASK_MR_FSL;
+	    rxc = 0;
+	    break;
+	  case M_LVHI_P_SS:
+	    vnum = 4;
+	    fsl = ((vtreg >> VF_SH_MR_VFSL) & VF_MASK_MR_VFSL) << 1;
+	    rxc = (vtreg >> VF_SH_MR_RXC) & VF_MASK_MR_RXC;
+	    break;
+	  }
+	if (rxc)
+	  vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_FSL)
+		  | (fsl << VF_SH_MR_IDX);
+	else
+	  vtreg_s = (mtx << VF_SH_MR_MTX) | (idx << VF_SH_MR_IDX)
+		  | (fsl << VF_SH_MR_FSL);
+
+
+	for (i = 0; i < vnum; i += 2) {
+	  f16v = ((vimm_expr[i + 1].X_add_number & 0xffff) << 16)
+	       | (vimm_expr[i].X_add_number & 0xffff);
+	  sprintf(f16v_str, "0x%08x", f16v);
+	  my_getExpression (&imm_expr, f16v_str);
+
+	  load_register (AT, &imm_expr, 0);
+	  macro_build ((expressionS *) NULL,
+		       "mtv", "t,?d0z", AT, vtreg_s);
+
+	  if (rxc)
+	    vtreg_s += (1 << VF_SH_MR_IDX);
+	  else
+	    vtreg_s += (1 << VF_SH_MR_FSL);
+	}
+
+	break;
+      }
+
     case M_LI_D:
       /* Check if we have a constant in IMM_EXPR.  If the GPRs are 64 bits
          wide, IMM_EXPR is the entire value.  Otherwise IMM_EXPR is the high
@@ -6672,6 +7018,27 @@
       move_register (dreg, sreg);
       break;
 
+    case M_VCMOV_S:
+      s = "vcmovt.s";
+      fmt = "?d0d,?s0s,?e";
+      goto vcmov;
+    case M_VCMOV_P:
+      s = "vcmovt.p";
+      fmt = "?d1d,?s1s,?e";
+      goto vcmov;
+    case M_VCMOV_T:
+      s = "vcmovt.t";
+      fmt = "?d2d,?s2s,?e";
+      goto vcmov;
+    case M_VCMOV_Q:
+      s = "vcmovt.q";
+      fmt = "?d3d,?s3s,?e";
+    vcmov:
+      macro_build ((expressionS *) NULL, s, fmt,
+		   vdreg, vsreg,
+		   (ip->insn_opcode >> VF_SH_MCOND) & VF_MASK_MCOND);
+      return;
+
 #ifdef LOSING_COMPILER
     default:
       /* Try and see if this is a new itbl instruction.
@@ -7348,6 +7715,39 @@
       move_register (treg, tempreg);
       break;
 
+    case M_ULV_S:
+      if (mips_opts.arch == CPU_ALLEGREX)
+	as_bad (_("opcode not supported on this processor"));
+      off = 3;
+      if (offset_expr.X_add_number >= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      if (! target_big_endian)
+	offset_expr.X_add_number += off;
+      macro_build (&offset_expr, "lwl", "t,o(b)",
+		   AT, (int) BFD_RELOC_LO16, breg);
+      if (! target_big_endian)
+	offset_expr.X_add_number -= off;
+      else
+	offset_expr.X_add_number += off;
+      macro_build (&offset_expr, "lwr", "t,o(b)",
+		   AT, (int) BFD_RELOC_LO16, breg);
+
+      macro_build ((expressionS *) NULL, "mtv", "t,?d0z",
+		   AT, vmreg);
+      break;
+
+    case M_ULV_Q:
+      off = 12;
+      if (offset_expr.X_add_number >= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      offset_expr.X_add_number += off;
+      macro_build (&offset_expr, "lvl.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      offset_expr.X_add_number -= off;
+      macro_build (&offset_expr, "lvr.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      return;
+
     case M_ULD_A:
       s = "ldl";
       s2 = "ldr";
@@ -7430,6 +7830,55 @@
       macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
       break;
 
+    case M_USV_S:
+      off = 3;
+      if (offset_expr.X_add_number >= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      macro_build ((expressionS *) NULL, "mfv", "t,?d0z",
+		   AT, vmreg);
+      if (mips_opts.arch != CPU_ALLEGREX)
+	{
+	  if (! target_big_endian)
+	    offset_expr.X_add_number += off;
+	  macro_build (&offset_expr, "swl", "t,o(b)",
+		       AT, (int) BFD_RELOC_LO16, breg);
+	  if (! target_big_endian)
+	    offset_expr.X_add_number -= off;
+	  else
+	    offset_expr.X_add_number += off;
+	  macro_build (&offset_expr, "swr", "t,o(b)",
+		       AT, (int) BFD_RELOC_LO16, breg);
+	}
+      else
+	{
+	  if (target_big_endian)
+	    offset_expr.X_add_number += off;
+	  while (off-- >= 0)
+	    {
+	      macro_build (&offset_expr, "sb", "t,o(b)",
+			   AT, (int) BFD_RELOC_LO16, breg);
+	      macro_build ((expressionS *) NULL, "ror",
+			   "d,w,<", AT, AT, 8);
+	      if (target_big_endian)
+		--offset_expr.X_add_number;
+	      else
+		++offset_expr.X_add_number;
+	    }
+	}
+      break;
+
+    case M_USV_Q:
+      off = 12;
+      if (offset_expr.X_add_number >= 0x8000 - off)
+	as_bad (_("operand overflow"));
+      offset_expr.X_add_number += off;
+      macro_build (&offset_expr, "svl.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      offset_expr.X_add_number -= off;
+      macro_build (&offset_expr, "svr.q", "?n3x,?o(b)",
+		   vmreg, (int) BFD_RELOC_LO16, breg);
+      return;
+
     case M_USD_A:
       s = "sdl";
       s2 = "sdr";
@@ -7817,6 +8266,103 @@
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+
+      /* VFPU fields */
+      case '?':
+	switch (c = *p++)
+	  {
+	  case '[': break;
+	  case ']': break;
+	  case 'y':
+	    {
+	      if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3'))
+		{
+		  as_bad (_("internal: bad mips opcode : %s %s"),
+			  opc->name, opc->args);
+		  return 0;
+		}
+	      p++;
+	    }
+	    break;
+
+	  case 'o': USE_BITS (VF_MASK_OFFSET,   VF_SH_OFFSET);  break;
+
+	  case 's':
+	  case 't':
+	  case 'd':
+	  case 'v':
+	  case 'x':
+	  case 'm':
+	  case 'n':
+	    {
+	      if ((*p != '0') && (*p != '1') && (*p != '2') && (*p != '3')
+		  && (*p != '5') && (*p != '6') && (*p != '7'))
+		{
+		  as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
+			  *p, opc->name, opc->args);
+		  return 0;
+		}
+	      p++;
+
+	      if ((*p != 's') && (*p != 't') && (*p != 'd')
+		  && (*p != 'y') && (*p != 'x') && (*p != 'z')
+		  && (*p != 'w') && (*p != 'm'))
+		{
+		  as_bad (_("internal: bad mips opcode (vreg type `?%c'): %s %s"),
+			  *(p - 1), opc->name, opc->args);
+		}
+	      p++;
+
+	      switch (c)
+		{
+		case 's': USE_BITS (VF_MASK_VS,  VF_SH_VS);     break;
+		case 't': USE_BITS (VF_MASK_VT,  VF_SH_VT);     break;
+		case 'd':
+		case 'v':
+		case 'x': USE_BITS (VF_MASK_VD,  VF_SH_VD);     break;
+		case 'm': USE_BITS (VF_MASK_VML, VF_SH_VML);
+			  USE_BITS (VF_MASK_VMH, VF_SH_VMH);    break;
+		case 'n': USE_BITS (VF_MASK_VNL, VF_SH_VNL);
+			  USE_BITS (VF_MASK_VNH, VF_SH_VNH);    break;
+		}
+	    }
+	    break;
+
+	  case 'f': USE_BITS (VF_MASK_CC,       VF_SH_CC);
+		    p++;					break;
+
+	  case 'a': USE_BITS (VF_MASK_CONST,    VF_SH_CONST);   break;
+	  case 'b': USE_BITS (VF_MASK_SCALE,    VF_SH_SCALE);   break;
+	  case 'c': USE_BITS (VF_MASK_BCOND,    VF_SH_BCOND);   break;
+	  case 'e': USE_BITS (VF_MASK_MCOND,    VF_SH_MCOND);   break;
+
+	  case 'i': USE_BITS (VF_MASK_WRAP,     VF_SH_WRAP);    break;
+
+	  case 'q': USE_BITS (VF_MASK_VCD,      VF_SH_VCD);     break;
+	  case 'r': USE_BITS (VF_MASK_VCS,      VF_SH_VCS);     break;
+
+	  case 'u': USE_BITS (VF_MASK_HFLOAT,   VF_SH_HFLOAT);  break;
+
+	  case 'w': USE_BITS (VF_MASK_ROT,      VF_SH_ROT);     break;
+	  case 'z': USE_BITS (VF_MASK_RWB,      VF_SH_RWB);     break;
+
+	  case '0': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '1': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '2': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '3': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '4': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '5': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '6': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+	  case '7': USE_BITS (VF_MASK_PFX,      VF_SH_PFX);     break;
+
+	  default:
+	    as_bad (_("internal: bad mips opcode (unknown extension operand type `?%c'): %s %s"),
+		    c, opc->name, opc->args);
+	    return 0;
+
+	  }
+	break;
+
       default:
 	as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
 		c, opc->name, opc->args);
@@ -7845,12 +8391,15 @@
   char c = 0;
   struct mips_opcode *insn;
   char *argsStart;
-  unsigned int regno;
+  unsigned int regno = 0;
   unsigned int lastregno = 0;
   unsigned int lastpos = 0;
   unsigned int limlo, limhi;
   char *s_reset;
   char save_c = 0;
+  unsigned int vdregno = 0xffff;
+  char vdregt = 0;
+  char vdregl = 0;
 
   insn_error = NULL;
 
@@ -8238,26 +8787,1171 @@
 	      s = expr_end;
 	      continue;
 
-	    case 'b':		/* base register */
-	    case 'd':		/* destination register */
-	    case 's':		/* source register */
-	    case 't':		/* target register */
-	    case 'r':		/* both target and source */
-	    case 'v':		/* both dest and source */
-	    case 'w':		/* both dest and target */
-	    case 'E':		/* coprocessor target register */
-	    case 'G':		/* coprocessor destination register */
-	    case 'K':		/* 'rdhwr' destination register */
-	    case 'x':		/* ignore register name */
-	    case 'z':		/* must be zero register */
-	    case 'U':           /* destination register (clo/clz).  */
-	      s_reset = s;
-	      if (s[0] == '$')
+	    /* VFPU fields */
+	    case '?':
+	    switch (*++args)
 		{
+	      case '[':
+	      case ']':
+		if (*s++ == *args)
+		  continue;
+		break;
 
-		  if (ISDIGIT (s[1]))
-		    {
-		      ++s;
+	      case 'y':		/* immediate separator */
+		++args;
+		vimm_expr[*args - '0'] = imm_expr;
+		voffset_expr[*args - '0'] = offset_expr;
+
+		imm_expr.X_op = O_absent;
+		offset_expr.X_op = O_absent;
+		imm_reloc[0] = BFD_RELOC_UNUSED;
+		imm_reloc[1] = BFD_RELOC_UNUSED;
+		imm_reloc[2] = BFD_RELOC_UNUSED;
+		offset_reloc[0] = BFD_RELOC_UNUSED;
+		offset_reloc[1] = BFD_RELOC_UNUSED;
+		offset_reloc[2] = BFD_RELOC_UNUSED;
+
+		continue;
+
+	      case 'o':		/* 16 bit offset */
+		/* Check whether there is only a single bracketed expression
+		   left.  If so, it must be the base register and the
+		   constant must be zero.  */
+		if (*s == '(' && strchr (s + 1, '(') == 0)
+		  {
+		    offset_expr.X_op = O_constant;
+		    offset_expr.X_add_number = 0;
+		    continue;
+		  }
+
+		/* If this value won't fit into a 16 bit offset, then go
+		   find a macro that will generate the 32 bit offset
+		   code pattern.  */
+		if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
+		    && (offset_expr.X_op != O_constant
+			|| offset_expr.X_add_number >= 0x8000