gcc-4.1.0.patch.svn-base

PSP开发环境(Linux) 包含PSPLINK 请自行选择需要安装的库及源代码

+       types[MIPS_SI_FTYPE_SF]
+ 	= build_function_type_list (intSI_type_node,
+ 				    float_type_node, NULL_TREE);
+     }
+
   if (TARGET_DSP)
     {
       V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
@@ -10557,6 +10673,10 @@
 
   switch (i)
     {
+     case 0:
+       emit_insn (GEN_FCN (icode) (0));
+       break;
+
     case 2:
       emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
       break;
@@ -10767,4 +10887,26 @@
     }
 }
 
+/* Expand a __builtin_allegrex_cache() function.  Make sure the passed
+   cache function code is less than 32.  */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist)
+{
+  rtx op0, op1;
+
+  op0 = mips_prepare_builtin_arg (icode, 0, &arglist);
+  op1 = mips_prepare_builtin_arg (icode, 1, &arglist);
+
+  if (GET_CODE (op0) == CONST_INT)
+    if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
+      {
+	error ("invalid function code '%d'", INTVAL (op0));
+	return const0_rtx;
+      }
+
+  emit_insn (GEN_FCN (icode) (op0, op1));
+  return target;
+}
+
 #include "gt-mips.h"
diff -burN gcc-4.1.0/gcc/config/mips/mips.h gcc-psp/gcc/config/mips/mips.h
--- gcc-4.1.0/gcc/config/mips/mips.h	2006-02-17 21:38:59.000000000 +0000
+++ gcc-psp/gcc/config/mips/mips.h	2006-05-07 18:37:54.000000000 +0100
@@ -59,6 +59,7 @@
   PROCESSOR_R9000,
   PROCESSOR_SB1,
   PROCESSOR_SR71000,
+  PROCESSOR_ALLEGREX,
   PROCESSOR_MAX
 };
 
@@ -194,6 +195,7 @@
 #define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
 
 /* Scheduling target defines.  */
 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
@@ -208,6 +210,7 @@
 #define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)
 #define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)
+#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)
 
 /* True if the pre-reload scheduler should try to create chains of
    multiply-add or multiply-subtract instructions.  For example,
@@ -578,6 +581,9 @@
                                  && !TARGET_MIPS5500                    \
 				 && !TARGET_MIPS16)
 
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE	(TARGET_ALLEGREX)
+
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
 #define ISA_HAS_8CC		(ISA_MIPS4				\
@@ -594,7 +600,8 @@
 
 /* ISA has conditional trap instructions.  */
 #define ISA_HAS_COND_TRAP	(!ISA_MIPS1				\
-				 && !TARGET_MIPS16)
+				 && !TARGET_MIPS16			\
+				 && !TARGET_ALLEGREX) 
 
 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
 #define ISA_HAS_MADD_MSUB       ((ISA_MIPS32				\
@@ -612,6 +619,7 @@
 #define ISA_HAS_CLZ_CLO         ((ISA_MIPS32				\
                                   || ISA_MIPS32R2			\
                                   || ISA_MIPS64				\
+                                  || TARGET_ALLEGREX			\
                                  ) && !TARGET_MIPS16)
 
 /* ISA has double-word count leading zeroes/ones instruction (not
@@ -659,6 +667,7 @@
                                      || TARGET_MIPS5400                 \
                                      || TARGET_MIPS5500                 \
                                      || TARGET_SR71K                    \
+                                     || TARGET_ALLEGREX                 \
                                      ))
 
 /* ISA has 64-bit rotate right instruction.  */
@@ -692,11 +701,13 @@
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
 #define ISA_HAS_SEB_SEH         (!TARGET_MIPS16                        \
                                  && (ISA_MIPS32R2                      \
+                                     || TARGET_ALLEGREX                \
                                      ))
 
 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 #define ISA_HAS_EXT_INS         (!TARGET_MIPS16                        \
                                  && (ISA_MIPS32R2                      \
+                                     || TARGET_ALLEGREX                \
                                      ))
 
 /* True if the result of a load is not available to the next instruction.
@@ -727,7 +738,8 @@
 #define ISA_HAS_HILO_INTERLOCKS	(ISA_MIPS32				\
 				 || ISA_MIPS32R2			\
 				 || ISA_MIPS64				\
-				 || TARGET_MIPS5500)
+				 || TARGET_MIPS5500			\
+				 || TARGET_ALLEGREX)
 
 /* Add -G xx support.  */
 
@@ -1143,6 +1155,11 @@
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = GET_MODE_BITSIZE (MODE), true)
 
+/* The [d]clz instructions have the natural values at 0.  */
+
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+  ((VALUE) = GET_MODE_BITSIZE (MODE), true)
+
 /* Standard register usage.  */
 
 /* Number of hardware registers.  We have:
diff -burN gcc-4.1.0/gcc/config/mips/mips.md gcc-psp/gcc/config/mips/mips.md
--- gcc-4.1.0/gcc/config/mips/mips.md	2005-07-29 18:25:27.000000000 +0100
+++ gcc-psp/gcc/config/mips/mips.md	2006-05-07 14:59:33.000000000 +0100
@@ -142,6 +142,21 @@
    (UNSPEC_MTHLIP		365)
    (UNSPEC_WRDSP		366)
    (UNSPEC_RDDSP		367)
+
+   ;; Sony ALLEGREX instructions
+   (UNSPEC_WSBH 		401)
+   (UNSPEC_WSBW 		402)
+
+   (UNSPEC_CLO			403)
+   (UNSPEC_CTO			404)
+
+   (UNSPEC_CACHE		405)
+   (UNSPEC_SYNC 		406)
+
+   (UNSPEC_CEIL_W_S		407)
+   (UNSPEC_FLOOR_W_S		408)
+   (UNSPEC_ROUND_W_S		409)
+
   ]
 )
 
@@ -1601,9 +1616,9 @@
 	   (mult:DI
 	      (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
-  "!TARGET_64BIT && ISA_HAS_MSAC"
+  "!TARGET_64BIT && (ISA_HAS_MSAC || TARGET_ALLEGREX)"
 {
-  if (TARGET_MIPS5500)
+  if (TARGET_MIPS5500 || TARGET_ALLEGREX)
     return "msub<u>\t%1,%2";
   else
     return "msac<u>\t$0,%1,%2";
@@ -1718,12 +1733,12 @@
 	 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		  (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
 	 (match_operand:DI 3 "register_operand" "0")))]
-  "(TARGET_MAD || ISA_HAS_MACC)
+  "(TARGET_MAD || ISA_HAS_MACC || TARGET_ALLEGREX)
    && !TARGET_64BIT"
 {
   if (TARGET_MAD)
     return "mad<u>\t%1,%2";
-  else if (TARGET_MIPS5500)
+  else if (TARGET_MIPS5500 || TARGET_ALLEGREX)
     return "madd<u>\t%1,%2";
   else
     /* See comment in *macc.  */
@@ -1995,6 +2010,32 @@
 ;;
 ;;  ....................
 ;;
+;;	FIND FIRST BIT INSTRUCTION
+;;
+;;  ....................
+;;
+
+(define_expand "ffs<mode>2"
+  [(set (match_operand:GPR 0 "register_operand" "")
+	(ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+  "ISA_HAS_CLZ_CLO"
+{
+  rtx r1, r2, r3, r4;
+
+  r1 = gen_reg_rtx (<MODE>mode);
+  r2 = gen_reg_rtx (<MODE>mode);
+  r3 = gen_reg_rtx (<MODE>mode);
+  r4 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_neg<mode>2 (r1, operands[1]));
+  emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+  emit_insn (gen_clz<mode>2 (r3, r2));
+  emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+  emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+  DONE;
+})
+;;
+;;  ....................
+;;
 ;;	NEGATION and ONE'S COMPLEMENT
 ;;
 ;;  ....................
@@ -4193,6 +4234,25 @@
   [(set_attr "type" "shift")
    (set_attr "mode" "<MODE>")])
 
+(define_expand "rotl<mode>3"
+  [(set (match_operand:GPR 0 "register_operand")
+      	(rotate:GPR (match_operand:GPR 1 "register_operand")
+		    (match_operand:SI 2 "arith_operand")))]
+  "ISA_HAS_ROTR_<MODE>"
+{
+  rtx temp;
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+  else
+    {
+      temp = gen_reg_rtx (<MODE>mode);
+      emit_insn (gen_neg<mode>2 (temp, operands[2]));
+    }
+  emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+  DONE;
+})
+
 ;;
 ;;  ....................
 ;;
@@ -5306,7 +5366,7 @@
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%T4\t%0,%z2,%1
     mov%t4\t%0,%z3,%1"
@@ -5336,8 +5396,12 @@
 	(if_then_else:GPR (match_dup 5)
 			  (match_operand:GPR 2 "reg_or_0_operand")
 			  (match_operand:GPR 3 "reg_or_0_operand")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
 {
+  if (ISA_HAS_INT_CONDMOVE
+      && GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_FLOAT)
+    FAIL;
+
   gen_conditional_move (operands);
   DONE;
 })
@@ -5428,3 +5492,6 @@
 ; The MIPS DSP Instructions.
 
 (include "mips-dsp.md")
+
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
diff -burN gcc-4.1.0/gcc/config/mips/psp.h gcc-psp/gcc/config/mips/psp.h
--- gcc-4.1.0/gcc/config/mips/psp.h	1970-01-01 01:00:00.000000000 +0100
+++ gcc-psp/gcc/config/mips/psp.h	2006-05-07 13:27:43.000000000 +0100
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+   Copyright (C) 2005 Free Software Foundation, Inc.
+   Contributed by Marcus R. Brown <[e-mail]>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"
diff -burN gcc-4.1.0/gcc/config/mips/t-allegrex gcc-psp/gcc/config/mips/t-allegrex
--- gcc-4.1.0/gcc/config/mips/t-allegrex	1970-01-01 01:00:00.000000000 +0100
+++ gcc-psp/gcc/config/mips/t-allegrex	2006-05-07 13:27:43.000000000 +0100
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = 
+MULTILIB_DIRNAMES = 
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff -burN gcc-4.1.0/gcc/config.gcc gcc-psp/gcc/config.gcc
--- gcc-4.1.0/gcc/config.gcc	2006-02-06 16:07:46.000000000 +0000
+++ gcc-psp/gcc/config.gcc	2006-05-07 13:27:40.000000000 +0100
@@ -406,12 +406,6 @@
       tm_defines="${tm_defines} FBSD_MAJOR=5" ;;
     *-*-freebsd6 | *-*-freebsd[6].*)
       tm_defines="${tm_defines} FBSD_MAJOR=6" ;;
-    *-*-freebsd7 | *-*-freebsd[7].*)
-      tm_defines="${tm_defines} FBSD_MAJOR=7" ;;
-    *-*-freebsd8 | *-*-freebsd[8].*)
-      tm_defines="${tm_defines} FBSD_MAJOR=8" ;;
-    *-*-freebsd9 | *-*-freebsd[9].*)
-      tm_defines="${tm_defines} FBSD_MAJOR=9" ;;
     *)
       echo 'Please update *-*-freebsd* in gcc/config.gcc'
       exit 1
@@ -756,11 +750,6 @@
         tmake_file=bfin/t-bfin-elf
         use_collect2=no
         ;;
-bfin*-uclinux*)
-	tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h bfin/uclinux.h"
-        tmake_file=bfin/t-bfin-elf
-        use_collect2=no
-        ;;
 bfin*-*)
 	tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h"
         tmake_file=bfin/t-bfin
@@ -1584,6 +1573,18 @@
 	tmake_file=mips/t-r3900
 	use_fixproto=yes
 	;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+	tm_file="elfos.h ${tm_file} mips/elf.h"
+	tmake_file=mips/t-allegrex
+	target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+	tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+	case ${target} in
+	mipsallegrex*-psp-elf*)	
+		tm_file="${tm_file} mips/psp.h"
+		;;
+	esac
+	use_fixproto=yes
+	;;
 mmix-knuth-mmixware)
 	need_64bit_hwint=yes
 	;;
diff -burN gcc-4.1.0/gcc/version.c gcc-psp/gcc/version.c
--- gcc-4.1.0/gcc/version.c	2005-03-16 06:04:10.000000000 +0000
+++ gcc-psp/gcc/version.c	2006-05-07 13:47:56.000000000 +0100
@@ -8,7 +8,7 @@
    in parentheses.  You may also wish to include a number indicating
    the revision of your modified compiler.  */
 
-#define VERSUFFIX ""
+#define VERSUFFIX " (PSPDEV 20060507)"
 
 /* This is the location of the online document giving instructions for
    reporting bugs.  If you distribute a modified version of GCC,
@@ -17,7 +17,7 @@
    forward us bugs reported to you, if you determine that they are
    not bugs in your modifications.)  */
 
-const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>";
+const char bug_report_url[] = "<URL:http://wiki.pspdev.org/psp:toolchain#bugs>";
 
 /* The complete version string, assembled from several pieces.
    BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile.  */