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+ else+ {+ mips_preferred_stack_align = (1 << i);+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;+ }+ }+ /* Default to working around R4000 errata only if the processor was selected explicitly. */ if ((target_flags_explicit & MASK_FIX_R4000) == 0@@ -9498,6 +9570,67 @@ DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE) }; +/* Builtin functions for the Sony ALLEGREX processor.++ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_'+ to maintain compatibility with Sony's ALLEGREX GCC port.++ Some of the builtins may seem redundant, but they are the same as the+ builtins defined in the Sony compiler. I chose to map redundant and+ trivial builtins to the original instruction instead of creating+ duplicate patterns specifically for the ALLEGREX (as Sony does). */++/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }++/* Same as the above, but mapped to an instruction that doesn't share the+ NAME. NAME is the name of the builtin without the builtin prefix. */+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \+ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }++/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are+ builtin_description fields. */+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }++/* Define a builtin with a specific function TYPE. */+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS }++static const struct builtin_description allegrex_bdesc[] =+{+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),++ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),++ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),++ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0)+};+ /* This helps provide a mapping from builtin function codes to bdesc arrays. */ @@ -9517,7 +9650,8 @@ static const struct bdesc_map bdesc_arrays[] = { { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_DEFAULT },- { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }+ { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },+ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX } }; /* Take the head of argument list *ARGLIST and convert it into a form@@ -9534,7 +9668,15 @@ value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0); mode = insn_data[icode].operand[op].mode; if (!insn_data[icode].operand[op].predicate (value, mode))+ { value = copy_to_mode_reg (mode, value);+ /* Check the predicate again. */+ if (!insn_data[icode].operand[op].predicate (value, mode))+ {+ error ("invalid argument to builtin function");+ return const0_rtx;+ }+ } *arglist = TREE_CHAIN (*arglist); return value;@@ -9591,7 +9733,10 @@ switch (type) { case MIPS_BUILTIN_DIRECT:- return mips_expand_builtin_direct (icode, target, arglist);+ return mips_expand_builtin_direct (icode, target, arglist, true);++ case MIPS_BUILTIN_DIRECT_NO_TARGET:+ return mips_expand_builtin_direct (icode, target, arglist, false); case MIPS_BUILTIN_MOVT: case MIPS_BUILTIN_MOVF:@@ -9606,6 +9751,9 @@ return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond, target, arglist); + case MIPS_BUILTIN_CACHE:+ return mips_expand_builtin_cache (icode, target, arglist);+ default: return 0; }@@ -9622,10 +9770,12 @@ tree V2SF_type_node; unsigned int offset; - /* We have only builtins for -mpaired-single and -mips3d. */- if (!TARGET_PAIRED_SINGLE_FLOAT)+ /* We have only builtins for -mpaired-single, -mips3d, and the Sony ALLEGREX. */+ if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_ALLEGREX) return; + if (TARGET_PAIRED_SINGLE_FLOAT)+ { V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode); types[MIPS_V2SF_FTYPE_V2SF]@@ -9684,6 +9834,45 @@ types[MIPS_DF_FTYPE_DF_DF] = build_function_type_list (double_type_node, double_type_node, double_type_node, NULL_TREE);+ }++ if (TARGET_ALLEGREX)+ {+ types[MIPS_SI_FTYPE_QI]+ = build_function_type_list (intSI_type_node,+ intQI_type_node,+ NULL_TREE);++ types[MIPS_SI_FTYPE_HI]+ = build_function_type_list (intSI_type_node,+ intHI_type_node,+ NULL_TREE);++ types[MIPS_SI_FTYPE_SI]+ = build_function_type_list (intSI_type_node,+ intSI_type_node,+ NULL_TREE);++ types[MIPS_SI_FTYPE_SI_SI]+ = build_function_type_list (intSI_type_node,+ intSI_type_node, intSI_type_node,+ NULL_TREE);++ types[MIPS_VOID_FTYPE_VOID]+ = build_function_type_list (void_type_node, void_type_node, NULL_TREE);++ types[MIPS_VOID_FTYPE_SI_SI]+ = build_function_type_list (void_type_node,+ intSI_type_node, intSI_type_node, NULL_TREE);++ types[MIPS_SF_FTYPE_SF]+ = build_function_type_list (float_type_node,+ float_type_node, NULL_TREE);++ types[MIPS_SI_FTYPE_SF]+ = build_function_type_list (intSI_type_node,+ float_type_node, NULL_TREE);+ } /* Iterate through all of the bdesc arrays, initializing all of the builtin functions. */@@ -9703,30 +9892,44 @@ /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the .md pattern and ARGLIST is the list of function arguments. TARGET,- if nonnull, suggests a good place to put the result. */+ if nonnull, suggests a good place to put the result.+ HAS_TARGET indicates the function must return something. */ static rtx-mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)+mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,+ bool has_target) { rtx ops[MAX_RECOG_OPERANDS];- int i;+ int i = 0; - target = mips_prepare_builtin_target (icode, 0, target);- for (i = 1; i < insn_data[icode].n_operands; i++)+ if (has_target)+ {+ /* We save target to ops[0]. */+ ops[0] = mips_prepare_builtin_target (icode, 0, target);+ i = 1;+ }++ /* We need to test if arglist is not zero. Some instructions have extra+ clobber registers. */+ for (; i < insn_data[icode].n_operands && arglist != 0; i++) ops[i] = mips_prepare_builtin_arg (icode, i, &arglist); - switch (insn_data[icode].n_operands)+ switch (i) {+ case 0:+ emit_insn (GEN_FCN (icode) (0));+ break;+ case 2:- emit_insn (GEN_FCN (icode) (target, ops[1]));+ emit_insn (GEN_FCN (icode) (ops[0], ops[1])); break; case 3:- emit_insn (GEN_FCN (icode) (target, ops[1], ops[2]));+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); break; case 4:- emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3]));+ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); break; default:@@ -9857,4 +10060,26 @@ return target; } +/* Expand a __builtin_allegrex_cache() function. Make sure the passed+ cache function code is less than 32. */++static rtx+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist)+{+ rtx op0, op1;++ op0 = mips_prepare_builtin_arg (icode, 0, &arglist);+ op1 = mips_prepare_builtin_arg (icode, 1, &arglist);++ if (GET_CODE (op0) == CONST_INT)+ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)+ {+ error ("invalid function code '%d'", INTVAL (op0));+ return const0_rtx;+ }++ emit_insn (GEN_FCN (icode) (op0, op1));+ return target;+}+ #include "gt-mips.h"diff -burN gcc-4.0.2/gcc/config/mips/mips.h gcc-psp/gcc/config/mips/mips.h--- gcc-4.0.2/gcc/config/mips/mips.h 2005-04-15 08:00:18.000000000 +0100+++ gcc-psp/gcc/config/mips/mips.h 2007-01-21 16:42:45.000000000 +0000@@ -59,7 +59,8 @@ PROCESSOR_R8000, PROCESSOR_R9000, PROCESSOR_SB1,- PROCESSOR_SR71000+ PROCESSOR_SR71000,+ PROCESSOR_ALLEGREX }; /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),@@ -308,6 +309,7 @@ #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) #define TARGET_SB1 (mips_arch == PROCESSOR_SB1) #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX) /* Scheduling target defines. */ #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)@@ -322,6 +324,7 @@ #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX) /* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example,@@ -798,6 +801,8 @@ N_("Specify cache flush function"), 0}, \ { "fix-vr4130", &mips_fix_vr4130_string, \ N_("Work around VR4130 mflo/mfhi errata"), 0}, \+ { "preferred-stack-boundary=", &mips_preferred_stack_boundary_string, \+ N_("Attempt to keep stack aligned to this power of 2"), 0}, \ } /* This is meant to be redefined in the host dependent files. */@@ -873,6 +878,9 @@ && !TARGET_MIPS5500 \ && !TARGET_MIPS16) +/* ISA has just the integer condition move instructions (movn,movz) */+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)+ /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ #define ISA_HAS_8CC (ISA_MIPS4 \@@ -889,7 +897,8 @@ /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \- && !TARGET_MIPS16)+ && !TARGET_MIPS16 \+ && !TARGET_ALLEGREX) /* ISA has integer multiply-accumulate instructions, madd and msub. */ #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \@@ -907,6 +916,7 @@ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \+ || TARGET_ALLEGREX \ ) && !TARGET_MIPS16) /* ISA has double-word count leading zeroes/ones instruction (not@@ -954,6 +964,7 @@ || TARGET_MIPS5400 \ || TARGET_MIPS5500 \ || TARGET_SR71K \+ || TARGET_ALLEGREX \ )) /* ISA has 64-bit rotate right instruction. */@@ -987,6 +998,13 @@ /* ISA includes the MIPS32r2 seb and seh instructions. */ #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ && (ISA_MIPS32R2 \+ || TARGET_ALLEGREX \+ ))++/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */+#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \+ && (ISA_MIPS32R2 \+ || TARGET_ALLEGREX \ )) /* True if the result of a load is not available to the next instruction.@@ -1017,7 +1035,8 @@ #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \- || TARGET_MIPS5500)+ || TARGET_MIPS5500 \+ || TARGET_ALLEGREX) /* Add -G xx support. */ @@ -1427,6 +1446,11 @@ /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND +/* The [d]clz instructions have the natural values at 0. */++#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \+ ((VALUE) = GET_MODE_BITSIZE (MODE), true)+ /* Standard register usage. */ /* Number of hardware registers. We have:@@ -2162,7 +2186,7 @@ `current_function_outgoing_args_size'. */ #define OUTGOING_REG_PARM_STACK_SPACE -#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)+#define STACK_BOUNDARY (mips_preferred_stack_boundary) #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 @@ -2318,7 +2342,7 @@ /* Treat LOC as a byte offset from the stack pointer and round it up to the next fully-aligned offset. */ #define MIPS_STACK_ALIGN(LOC) \- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)+ ((LOC) + (mips_preferred_stack_align - 1) & -(mips_preferred_stack_align)) ⌨️ 快捷键说明
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