📄 tx_ill.s
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ADD a2, a2, a3 ; Calculate start of IRQ stack
BIC a2, a2, #3 ; Ensure long word alignment
SUB a2, a2, #4 ; Backup one word
MOV sp, a2 ; Setup IRQ stack pointer
MOV a1, #SVC_MODE ; Build SVC mode CPSR
MSR CPSR_c, a1 ; Enter SVC mode
LDR a4, [pc, #SYS_STACK_PTR-.-8] ; Pickup stack pointer
STR a2, [a4, #0] ; Save the system stack
MOV sp, a2 ; Use IRQ stack during initialization
MOV fp, #0 ; Clear frame pointer
MOV sl, #0 ; Clear stack limit
;
; /* Call the C main routine. */
;
BL initiate
BL main ; Call main function
exit
B exit ; Just sit here!
;
;
;/**************************************************************************/
;/* */
;/* FUNCTION RELEASE */
;/* */
;/* _tx_initialize_low_level ARM7/ARM */
;/* 3.0e */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Express Logic, Inc. */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function is responsible for any low-level processor */
;/* initialization, including setting up interrupt vectors, saving the */
;/* system stack pointer, finding the first available memory address, */
;/* and setting up parameters for the system's timer thread. */
;/* */
;/* INPUT */
;/* */
;/* None */
;/* */
;/* OUTPUT */
;/* */
;/* None */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* CALLED BY */
;/* */
;/* _tx_initialize_kernel_enter ThreadX entry function */
;/* */
;/* RELEASE HISTORY */
;/* */
;/* DATE NAME DESCRIPTION */
;/* */
;/* 06-15-1997 William E. Lamie Initial Version 3.0 */
;/* 11-11-1997 William E. Lamie Modified comment(s), */
;/* resulting in version 3.0b. */
;/* 03-01-1998 William E. Lamie Modified comment(s), */
;/* resulting in version 3.0d. */
;/* 01-01-1999 William E. Lamie Modified comment(s), */
;/* resulting in version 3.0e. */
;/* */
;/**************************************************************************/
;VOID _tx_initialize_low_level(VOID)
;{
EXPORT _tx_initialize_low_level
_tx_initialize_low_level
;
; /* Save the system stack pointer. */
; _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
;
LDR a2, [pc, #SYS_STACK_PTR-.-8] ; Pickup address of system stack ptr
LDR a1, [a2, #0] ; Pickup system stack
ADD a1, a1, #4 ; Increment to next free word
;
; /* Pickup the first available memory address. */
;
; /* Allocate space for the timer thread's stack. */
; _tx_timer_stack_start = first_available_memory;
; _tx_timer_stack_size = stack_size;
; _tx_timer_priority = 0;
;
LDR a2, [pc, #TIMER_STACK-.-8] ; Pickup timer stack ptr address
LDR a4, [pc, #TIMER_STACK_SIZE-.-8] ; Pickup timer stack size address
LDR a3, [pc, #TIM_STACK_SIZE-.-8] ; Pickup actual stack size
STR a1, [a2, #0] ; Store timer stack base
STR a3, [a4, #0] ; Store timer stack size
ADD a1, a1, a3 ; New free memory address
LDR a2, [pc, #TIMER_PRIORITY-.-8] ; Pickup timer priority address
MOV a3, #0 ; Build timer thread priority
STR a3, [a2, #0] ; Store timer thread priority
;
; /* Save the first available memory address. */
; _tx_initialize_unused_memory = (VOID_PTR) System Stack + Timer Stack;
;
LDR a3, [pc, #UNUSED_MEMORY-.-8] ; Pickup unused memory ptr address
STR a1, [a3, #0] ; Save first free memory address
; /* RUN RTC */
; LDR r0,=ILR
; LDR r2,=0x01
; STR r2,[r0,#0]
; LDR r0,=CIIR
; LDR r2,=0x01
; STR r2,[r0,#0]
LDR r0,=CCR
LDR r2,=0x01
STR r2,[r0,#0]
;/* Enable TC0 Interrupt */
LDR r0,=T0IR
LDR r2,=0x01
STR r2,[r0,#0]
LDR r0,=T0TCR ; T0 Enable
LDR r2,=0x03
STR r2,[r0,#0]
LDR r0,=T0TCR ; T0 Reset
LDR r2,=0x01
STR r2,[r0,#0]
LDR r0,=VICVectAddr
LDR r2,=0x0
STR r2,[r0,#0]
LDR r0,=VICIntEnable
LDR r2,=0x10
STR r2,[r0,#0]
; /* Done, return to caller. */
;
MOV pc, lr ; Return to caller
;}
;
;
;/* Define shells for each of the interrupt vectors. */
;
EXPORT __tx_undefined
__tx_undefined
; B __tx_undefined ; Undefined handler
ldr pc, =0x10000dc
;
EXPORT __tx_swi_interrupt
__tx_swi_interrupt
; B __tx_swi_interrupt ; Software interrupt handler
ldr pc, =0x10000dc
;
EXPORT __tx_prefetch_handler
__tx_prefetch_handler
; B __tx_prefetch_handler ; Prefetch exeception handler
ldr pc, =0x10000dc
;
EXPORT __tx_abort_handler
__tx_abort_handler
; B __tx_abort_handler ; Abort exception handler
ldr pc, =0x10000Dc
;
EXPORT __tx_reserved_handler
__tx_reserved_handler
; B __tx_reserved_handler ; Reserved exception handler
ldr pc, =0x10000dc
;
EXPORT __tx_irq_handler
EXPORT __tx_irq_processing_return
__tx_irq_handler
;
; /* Jump to context save to save system context. */
B _tx_thread_context_save
__tx_irq_processing_return
;
; /* At this point execution is still in the IRQ mode. The CPSR, point of
; interrupt, and all C scratch registers are available for use. In
; addition, IRQ interrupts may be re-enabled if nested IRQ interrupts
; are desired. */
;
; /* For debug purpose, execute the timer interrupt processing here. In
; a real system, some kind of status indication would have to be checked
; before the timer interrupt handler could be called. */
IMPORT irq_handler
BL irq_handler
; BL _tx_timer_interrupt ; Timer interrupt handler
;
; /* Jump to context restore to restore system context. */
B _tx_thread_context_restore
;
EXPORT __tx_fiq_handler
__tx_fiq_handler
B __tx_fiq_handler ; FIQ interrupt handler
;
;
SYS_STACK_PTR
DCD _tx_thread_system_stack_ptr
FIQ_STACK_SIZE
DCD 512 ; Keep 4-byte alignment
SYS_STACK_SIZE
DCD 1024 ; Keep 4-byte alignment
TIM_STACK_SIZE
DCD 1024 ; Timer stack size
UNUSED_MEMORY
DCD _tx_initialize_unused_memory
TIMER_STACK
DCD _tx_timer_stack_start
TIMER_STACK_SIZE
DCD _tx_timer_stack_size
TIMER_PRIORITY
DCD _tx_timer_priority
;/*- Default Interrupt Handlers*/
;; IMPORT spurious_handler
AicData
DCD VICVectAddr_Base ; AIC Base Address
PtDefaultHandler
DCD __tx_irq_handler
END
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