ci8534tm.v

Analog signals are represented by 64 bit buses. They are converted to real and from real representa

    //-- Converting signals from its real equivalent
    assign ifs                  = $realtobits(rl_ifs);
    assign icm                  = $realtobits(rl_icm);
    //--
    //-- Behaviour --------------------------------------------------------

//rtl_synthesis on
//ambit synthesis on
//ambit translate on
//synopsys translate_on
//surelint translate_on

endmodule // ci8534tm_iqdac

//rtl_synthesis off
//ambit synthesis off
//ambit translate off
//synopsys translate_off
//surelint translate_off

//----------------------------------------------------------------------
//  Module       : ci8534tmiqdac_dac10b
//  Contact      : [e-mail]
//  Description  : Implements a 10bit dac with current output
//----------------------------------------------------------------------

module ci8534tmiqdac_dac10b (
    clk,    // clock signal
    dacb,   // input bits for dac
    endac,  // enable control for dac
    ibias,  // common mode output current
    ifs,    // full scale output current
    ioutn,  // negative output current
    ioutp   // positive output current
);

    //-- Parameters  ---------------------------------------------------
    //--
    parameter TDELAY = 0.0;     // (ns) delay for output after clk negedge
    parameter TSETTLE = 0.0;    // (ns) settling time
    //--
    //-- Parameters  ---------------------------------------------------

    //-- Ports  --------------------------------------------------------
    //--

    input clk;          wire clk;
    input [9:0] dacb;   wire [9:0] dacb;
    input endac;        wire endac;
    input ibias;        wire [63:0] ibias;      real rl_ibias;
    input ifs;          wire [63:0] ifs;        real rl_ifs;
    output ioutn;       reg  [63:0] ioutn;      real rl_ioutn;
    output ioutp;       reg  [63:0] ioutp;      real rl_ioutp;

    //--
    //-- Ports  --------------------------------------------------------

    //-- Variables -----------------------------------------------------
    //--

    reg [9:0] bin;
    real rl_iout;
    real rl_frac_iout;
    wire [63:0] ioutn_tmp;      real rl_ioutn_tmp;
    wire [63:0] ioutp_tmp;      real rl_ioutp_tmp;
    wire [63:0] ioutn_int;
    wire [63:0] ioutp_int;
    //--
    //-- Variables -----------------------------------------------------

    //-- Specify -------------------------------------------------------
    //--
    reg notf_setup;
    reg notf_hold;

    specify
        specparam thold_clk_b  = 1.0;        // (ns) Input word hold time
        specparam tsetup_clk_b = 0.5;        // (ns) Input word setup time

        $setup(dacb[9], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[8], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[7], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[6], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[5], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[4], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[3], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[2], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[1], negedge clk &&& endac, tsetup_clk_b, notf_setup);
        $setup(dacb[0], negedge clk &&& endac, tsetup_clk_b, notf_setup);

        $hold(negedge clk &&& endac, dacb[9], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[8], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[7], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[6], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[5], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[4], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[3], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[2], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[1], thold_clk_b,notf_hold);
        $hold(negedge clk &&& endac, dacb[0], thold_clk_b,notf_hold);
    endspecify

    //--
    //-- Specify -------------------------------------------------------

    //-- Behaviour -----------------------------------------------------
    //--

    // Output current determination related to Full scale
    initial assign rl_iout = rl_ifs*rl_frac_iout;

    // input word latching
    always @(negedge clk)
    begin
        if (endac == 1)
        begin
            bin = dacb;
            rl_frac_iout <= @(posedge clk) $itor(bin)/1023;
        end
    end

    always @(negedge endac)
    begin
        rl_frac_iout = 0.0;
        bin = 512;
    end

    // Output signal generation
    always @(rl_ibias or rl_ifs or rl_iout)
    begin
        rl_ioutn_tmp = rl_iout;
        rl_ioutp_tmp = rl_ifs - rl_iout;
    end

    // Output signal conversion
    assign ioutn_int = (endac === 1'b1) ? rl_ioutn_tmp >= 0.0 ? ioutn_tmp : $realtobits(0.0) : $realtobits(0.0);
    assign ioutp_int = (endac === 1'b1) ? rl_ioutp_tmp >= 0.0 ? ioutp_tmp : $realtobits(0.0) : $realtobits(0.0);

    //-- Output buffering
    always @(ioutn_int or endac)
    begin
        if (endac === 1'b1)
            ioutn   <= #(TDELAY+TSETTLE) ioutn_int;
        else
            ioutn   <= #(TDELAY+TSETTLE) $realtobits(0.0);
    end
    always @(ioutp_int or endac)
    begin
        if (endac === 1'b1)
            ioutp   <= #(TDELAY+TSETTLE) ioutp_int;
        else
            ioutp   <= #(TDELAY+TSETTLE) $realtobits(0.0);
    end

    //-- Converting ports to its real equivalent
    initial assign rl_ibias     = $bitstoreal(ibias);
    initial assign rl_ifs       = $bitstoreal(ifs);
    initial assign rl_ioutn     = $bitstoreal(ioutn);
    initial assign rl_ioutp     = $bitstoreal(ioutp);

    //-- Converting signals to its real equivalent
    assign ioutn_tmp            = $realtobits(rl_ioutn_tmp);
    assign ioutp_tmp            = $realtobits(rl_ioutp_tmp);
    //--
    //-- Behaviour -----------------------------------------------------

endmodule // ci8534tmiqdac_dac10b

//----------------------------------------------------------------------
//
// File         : ci8534tmpowerupcontrol.v
//
// Author       : Joao Serras
// Contact      : [e-mail]
//
//----------------------------------------------------------------------
//
//                    ChipIdea Microeletronica S.A.
//                 TagusPark, Ed. Inovacao IV, sala 733
//                      2780-920 Oeiras, PORTUGAL
//               Tel: [phone]    Fax: [phone]
//       Mail: [e-mail]     URL: http://www.chipidea.com
//
//----------------------------------------------------------------------
//
// Cell/Project  : ci8534tmpowerupcontrol
// Creation date : Jan  7 14:32:11 2004
// Version       : 2.0
// Simulator     : verilog/Modelsim 5.5e
// Language      : verilog
// Description   : Verilog model for the power up control behaviour
// Related files :
// Special notes :
//
//  * Analog signals are represented by 64 bit buses. They are converted
//    to real and from real representation using PLI functions
//    $bitstoreal and $realtobits respectively
//    ex:
//      reg[63:0] a;
//      reg[63:0] b;
//      real rl_a;
//      real rl_b;
//      (...)
//      rl_a = $bitstoreal(a);
//      (...)
//      b = $realtobits(rl_b);
//
//----------------------------------------------------------------------
//
// History:
// Date        Who       Description
// 2004/03/11  jserras   created
// 2004/03/15  jserras   fixed bug of normal->shutdown->normal when
//                       enable caused shutdown
//----------------------------------------------------------------------


//----------------------------------------------------------------------
//  Module       : ci8534tmpowerupcontrol
//  Description  : power up control timing for stanby to normal and from
//                 shutdown to normal modes
//----------------------------------------------------------------------
`timescale 1ns/10ps

module ci8534tmpowerupcontrol (
    ctr,            // control bits
    enable,         // enable control
    on              // power up done
);

    //-- Parameters  ---------------------------------------------------
    //--
    parameter WAKEUPSTB = 0;     // (ns) wake up time from standby
    parameter WAKEUPSHT = 0;     // (ns) wake up time from shutdown
    //--
    //-- Parameters  ---------------------------------------------------

    //-- Ports  --------------------------------------------------------
    //--
    input ctr;          wire [1:0] ctr;
    input enable;       wire enable;
    output on;          wire on;
    //--
    //-- Ports  --------------------------------------------------------

    //-- Variables -----------------------------------------------------
    //--
    real rl_pmode;    // previous mode 0 - shutdown; 1 - standby; 2 - normal
    real rl_cmode;    // current mode 0 - shutdown; 1 - standby; 2 - normal
    real rl_standby;
    real rl_shutdown;
    real ok;
    //--
    //-- Variables -----------------------------------------------------

    //-- Behaviour -----------------------------------------------------
    //--

    initial begin
        rl_cmode =0;
        rl_pmode =0;
        ok = 0;
    end

    // reset
    always @(negedge enable) begin
        rl_cmode = 0;
        rl_pmode = 0;
        ok = 0;
    end

    // mode change
    always @(ctr or enable)
    begin
        if (enable == 1)
        begin
            rl_pmode = rl_cmode;
            casez (ctr)
                2'b00 :     rl_cmode = 0;
                2'b01 :     rl_cmode = 1;
                2'b11 :     rl_cmode = 2;
                default :   rl_cmode = 0;
            endcase
            // power down mode
            if (rl_cmode == 0 || rl_cmode == 1)
                ok = 0;
            // mark begining of standby to normal operation
            if (rl_pmode == 1 && rl_cmode == 2)
                rl_standby = $realtime;
            // mark begining of shutdown to normal operation
            if (rl_pmode == 0 && rl_cmode == 2)
                rl_shutdown = $realtime;
            // mark begining of shutdown to standby operation
            if (rl_pmode == 0 && rl_cmode == 1)
                rl_shutdown = $realtime;
        end
    end

    always #(1) begin
        wait(enable == 1 && rl_cmode == 2 && ok == 0);
        if (rl_pmode == 1 &&
            ($realtime-rl_standby >= WAKEUPSTB) &&
            ($realtime-rl_shutdown >= WAKEUPSHT))
            ok = 1;
        if (rl_pmode == 0 && ($realtime-rl_shutdown >= WAKEUPSHT))
            ok = 1;
    end

    assign on = (ok == 1) ? 1'b1 : 1'b0;

    //--
    //-- Behaviour -----------------------------------------------------

endmodule // ci8534tmpowerupcontrol

//rtl_synthesis on
//ambit synthesis on
//ambit translate on
//synopsys translate_on
//surelint translate_on