ci8534tm.v

Analog signals are represented by 64 bit buses. They are converted to real and from real representa

//
//  * Analog signals are represented by 64 bit buses. They are converted
//    to real and from real representation using PLI functions
//    $bitstoreal and $realtobits respectively
//    ex:
//      reg[63:0] a;
//      reg[63:0] b;
//      real rl_a;
//      real rl_b;
//      (...)
//      rl_a = $bitstoreal(a);
//      (...)
//      b = $realtobits(rl_b);
//
//-------------------------------------------------------------------------
//
// History:
// Date       Who      Description
// 2006/10/11 vhugo    Created this file.
// 
//-------------------------------------------------------------------------
`timescale 1ns/10ps

module ci8534tm (
    agnd,       // Analog ground
    avdd,       // Analog power supply
    dgnd,       // Digital ground
    dgnd1,      // Cleaner digital ground
    dvdd,       // Digital power supply
    dvdd1,      // Cleaner digital power supply
    iref,       // Reference Current
    vbg,        // Bandgap Reference Voltage Input
    bypidac,    // External Reference Current Enable
    clk,        // Clock signal
    dacib0,     // Digital Input bit for channel I
    dacib1,     // Digital Input bit for channel I
    dacib2,     // Digital Input bit for channel I
    dacib3,     // Digital Input bit for channel I
    dacib4,     // Digital Input bit for channel I
    dacib5,     // Digital Input bit for channel I
    dacib6,     // Digital Input bit for channel I
    dacib7,     // Digital Input bit for channel I
    dacib8,     // Digital Input bit for channel I
    dacib9,     // Digital Input bit for channel I
    dacqb0,     // Digital Input bit for channel Q
    dacqb1,     // Digital Input bit for channel Q
    dacqb2,     // Digital Input bit for channel Q
    dacqb3,     // Digital Input bit for channel Q
    dacqb4,     // Digital Input bit for channel Q
    dacqb5,     // Digital Input bit for channel Q
    dacqb6,     // Digital Input bit for channel Q
    dacqb7,     // Digital Input bit for channel Q
    dacqb8,     // Digital Input bit for channel Q
    dacqb9,     // Digital Input bit for channel Q
    enctr0,     // Enable control pin for analog biasing test
    enctr1,     // Enable control pin for analog biasing test
    enctr2,     // Enable control pin for analog biasing test
    endaci,     // Enable control pin to power up the DAC
    endacq,     // Enable control pin to power up the DAC
    ifs0,       // Programmable output full scale current
    ifs1,       // Programmable output full scale current
    ifs2,       // Programmable output full scale current
    ifs3,       // Programmable output full scale current
    enctr3,     // Control pin for analog biasing test
    ioutni,     // Negative Output Current for channel I
    ioutnq,     // Negative Output Current for channel Q
    ioutpi,     // Positive Output Current for channel I
    ioutpq      // Positive Output Current for channel Q
);


    //--
    parameter REFRES = 76.8e3;          // (ohm) Reference current resistor
    // Do not modify the following parameters:
    parameter AVDDMIN = 3.00;           // (V) Minimum avdd voltage
    parameter AVDDMAX = 3.60;           // (V) Maximum avdd voltage
    parameter DVDDMIN = 1.08;           // (V) Minimum dvdd voltage
    parameter DVDDMAX = 1.32;           // (V) Maximum dvdd voltage
    parameter TDELAY = 3.0;             // (ns) Analog output delay
    parameter TSETTLE = 0.0;            // (ns) output settling time
    parameter WAKEUPSTB = 2_000;        // (ns) wake up time from standby
    parameter WAKEUPSHT = 2_000;        // (ns) wake up time from shutdown
    parameter VBGMIN = 1.2*0.8;         // (V) Minimum bandgap voltage
    parameter VBGMAX = 1.2*1.2;         // (V) Maximum bandgap voltage
    parameter IBIAS     = 1.2/REFRES;   // (A) Bias current
    parameter IBIASMAX  = IBIAS*2.1;    // (A) Maximum ibias current
    parameter IBIASMIN  = IBIAS*0.4;    // (A) Minimum ibias current
    //--
    //-- Parameters -------------------------------------------------------

//rtl_synthesis on
//ambit synthesis on
//ambit translate on
//synopsys translate_on
//surelint translate_on

    //-- Ports ------------------------------------------------------------
    //--
    inout        agnd;
    inout        avdd;
    inout        dgnd;
    inout        dgnd1;
    inout        dvdd;
    inout        dvdd1;
    inout        iref;
    inout        vbg;
    input        bypidac;
    input        clk;
    input        dacib0;
    input        dacib1;
    input        dacib2;
    input        dacib3;
    input        dacib4;
    input        dacib5;
    input        dacib6;
    input        dacib7;
    input        dacib8;
    input        dacib9;
    input        dacqb0;
    input        dacqb1;
    input        dacqb2;
    input        dacqb3;
    input        dacqb4;
    input        dacqb5;
    input        dacqb6;
    input        dacqb7;
    input        dacqb8;
    input        dacqb9;
    input        enctr0;
    input        enctr1;
    input        enctr2;
    input        endaci;
    input        endacq;
    input        ifs0;
    input        ifs1;
    input        ifs2;
    input        ifs3;
    output        enctr3;
    output        ioutni;
    output        ioutnq;
    output        ioutpi;
    output        ioutpq;
    //--
    //-- Ports ------------------------------------------------------------

//rtl_synthesis off
//ambit synthesis off
//ambit translate off
//synopsys translate_off
//surelint translate_off

    //-- Variables --------------------------------------------------------
    //--
    wire [63:0] agnd;           real rl_agnd;
    wire [63:0] avdd;           real rl_avdd;
    wire [63:0] dgnd;           real rl_dgnd;
    wire [63:0] dgnd1;          real rl_dgnd1;
    wire [63:0] dvdd;           real rl_dvdd;
    wire [63:0] dvdd1;          real rl_dvdd1;
    wire [63:0] iref;           real rl_iref;
    wire [63:0] vbg;            real rl_vbg;
    wire        bypidac;
    wire        clk;
    wire        dacib0;
    wire        dacib1;
    wire        dacib2;
    wire        dacib3;
    wire        dacib4;
    wire        dacib5;
    wire        dacib6;
    wire        dacib7;
    wire        dacib8;
    wire        dacib9;
    wire        dacqb0;
    wire        dacqb1;
    wire        dacqb2;
    wire        dacqb3;
    wire        dacqb4;
    wire        dacqb5;
    wire        dacqb6;
    wire        dacqb7;
    wire        dacqb8;
    wire        dacqb9;
    wire        enctr0;
    wire        enctr1;
    wire        enctr2;
    wire        endaci;
    wire        endacq;
    wire        ifs0;
    wire        ifs1;
    wire        ifs2;
    wire        ifs3;
    wire        enctr3;
    wire [63:0] ioutni;         real rl_ioutni;
    wire [63:0] ioutnq;         real rl_ioutnq;
    wire [63:0] ioutpi;         real rl_ioutpi;
    wire [63:0] ioutpq;         real rl_ioutpq;

    wire        powerOnI;
    wire        powerOnQ;
    wire        powerOk;
    wire  [3:0] ifs_ctrl;
    wire [63:0] ifs;            real rl_ifs;
    wire [63:0] icm;            real rl_icm;
    real        rl_mult;
    //--
    //-- Variables --------------------------------------------------------

    //-- Instances --------------------------------------------------------
    //--
    ci8534tmpowerupcontrol
    #(WAKEUPSTB,WAKEUPSHT)
    POWERUPI (
        .ctr({2{endaci}}),
        .enable(powerOk),
        .on(powerOnI)
    );

    ci8534tmpowerupcontrol
    #(WAKEUPSTB,WAKEUPSHT)
    POWERUPQ (
        .ctr({2{endacq}}),
        .enable(powerOk),
        .on(powerOnQ)
    );

    // DAC I
    ci8534tmiqdac_dac10b
    #(TDELAY, TSETTLE)
    DACI (
        .clk(clk),
        .dacb({~dacib9,dacib8,dacib7,dacib6,dacib5,dacib4,dacib3,dacib2,dacib1,dacib0}),
        .endac(powerOnI & endaci),
        .ibias(icm),
        .ifs(ifs),
        .ioutn(ioutni),
        .ioutp(ioutpi)
    );

    // DAC Q
    ci8534tmiqdac_dac10b
    #(TDELAY, TSETTLE)
    DACQ (
        .clk(clk),
        .dacb({~dacqb9,dacqb8,dacqb7,dacqb6,dacqb5,dacqb4,dacqb3,dacqb2,dacqb1,dacqb0}),
        .endac(powerOnQ & endacq),
        .ibias(icm),
        .ifs(ifs),
        .ioutn(ioutnq),
        .ioutp(ioutpq)
    );					
	
//	//---Test  signals of the iouti and the ioutq------------------
//	real iouti,ioutq;
//	always @(rl_ioutni or rl_ioutpi)
//		iouti<=rl_ioutpi-rl_ioutni;
//	always @(rl_ioutnq or rl_ioutpq)
//		ioutq<=rl_ioutpq-rl_ioutnq;
//	//-------------------------------------------------------------
	
	
    //--
    //-- Instances --------------------------------------------------------

    //-- Behaviour --------------------------------------------------------
    //--
    //-- 
    //-- Full scale current selection
    assign ifs_ctrl = {ifs3,ifs2,ifs1,ifs0};
    always @(ifs_ctrl)
    begin
        casex (ifs_ctrl)
            4'b0000 : rl_mult = 640.0;
            4'b0001 : rl_mult = 512.0;
            4'b001? : rl_mult = 384.0;
            4'b01?? : rl_mult = 256.0;
            4'b1??? : rl_mult = 128.0;
        endcase
    end

    //-- Iref generation
    assign iref = bypidac === 1'b1 ? {64{1'bz}} : $realtobits(powerOk*rl_vbg/REFRES);

    //-- Full scale output current
    initial assign rl_ifs = rl_iref*rl_mult;

    //-- Common mode output current
    initial assign rl_icm = rl_ifs/10.0;

    //-- Not implemented
    assign enctr3 = 1'b0;

    //-- Verification of power Up conditions
    assign powerOk = (
        rl_avdd  -  rl_agnd <= AVDDMAX &&
        rl_avdd  -  rl_agnd >= AVDDMIN &&
        rl_dvdd  -  rl_dgnd <= DVDDMAX &&
        rl_dvdd  -  rl_dgnd >= DVDDMIN &&
        rl_dvdd1 - rl_dgnd1 <= DVDDMAX &&
        rl_dvdd1 - rl_dgnd1 >= DVDDMIN &&
        rl_vbg   -  rl_agnd <= VBGMAX  &&
        rl_vbg   -  rl_agnd >= VBGMIN  &&
        (
            bypidac === 1'b0 ||
            rl_iref  >= IBIASMIN &&
            rl_iref  <= IBIASMAX
        ) &&
        enctr2 | enctr1 | enctr0 === 1'b0
    );

    //-- Converting ports to its real equivalent
    initial assign rl_agnd      = $bitstoreal(agnd);
    initial assign rl_avdd      = $bitstoreal(avdd);
    initial assign rl_dgnd      = $bitstoreal(dgnd);
    initial assign rl_dgnd1     = $bitstoreal(dgnd1);
    initial assign rl_dvdd      = $bitstoreal(dvdd);
    initial assign rl_dvdd1     = $bitstoreal(dvdd1);
    initial assign rl_iref      = $bitstoreal(iref);
    initial assign rl_vbg       = $bitstoreal(vbg);
    initial assign rl_ioutni    = $bitstoreal(ioutni);
    initial assign rl_ioutnq    = $bitstoreal(ioutnq);
    initial assign rl_ioutpi    = $bitstoreal(ioutpi);
    initial assign rl_ioutpq    = $bitstoreal(ioutpq);