fifotop.v

来自「FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。」· Verilog 代码 · 共 47 行

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2005 by DTK Corporation
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
// This is the top level file ofof the fast FIFO 
//controller reference design.
//
// --------------------------------------------------------------------
//
// Revision History : 
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release
// --------------------------------------------------------------------
`timescale 1ns / 100ps

module fifoTop(empty,full,dout,rst,wr_clk,wren,din,rd_clk,rden);
`include "FIFOPar.v"
output empty,full;
output[`FIFODataWidth-1:0] dout;
input rst,wr_clk,wren,rd_clk,rden;
input[`FIFODataWidth-1:0] din;
wire empty,full,wr_page,rd_page,dpwren;
wire [`FIFOAddrDepth-1:0] dpwraddress,dprdaddress;
wire [`FIFODataWidth-1:0] dpdin,dpdout;

FIFOdpRAMInterface dpraminterface(.full(full),.empty(empty),.dpwren(dpwren),
                   .dpdin(dpdin),.dpwraddress(dpwraddress),.dprdaddress(dprdaddress),
                   .dout(dout),.rst(rst),.wren(wren),.wr_clk(wr_clk),
                   .din(din),.rden(rden),.rd_clk(rd_clk),.dpdout(dpdout));

dpram dualportram(
	.data(dpdin),
	.wren(dpwren),
	.wraddress(dpwraddress),
	.rdaddress(dprdaddress),
	.wrclock(wr_clk),
	.rdclock(rd_clk),
	.q(dpdout));


endmodule