fifopar.v

来自「FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。」· Verilog 代码 · 共 46 行

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2005 by DTK Corporation
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
// This file contains the parameters used in the fast FIFO controller
// reference design.
//
// --------------------------------------------------------------------
//
// Revision History : 
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release
// --------------------------------------------------------------------


parameter tDLY = 2; // 2ns delay for simulation purpose

//data width of the dual port RAM 
`ifdef FIFODataWidth          //data width =16;
`undef FIFODataWidth
`endif
`define FIFODataWidth  16 

//the dual port RAM capacitibility
`ifdef FIFOCap                // capacity: 64*1024=65536bits;
`undef FIFOCap
`endif
`define FIFOCap 64*1024

// maxium address value of the dual port RAM
`ifdef FIFOMaxAddressValue
`undef FIFOMaxAddressValue
`endif
`define FIFOMaxAddressValue (`FIFOCap/`FIFODataWidth)-1

//address depth of the dual port RAM
`ifdef FIFOAddrDepth          // address depth=12 ;
`undef FIFOAddrDepth
`endif
`define FIFOAddrDepth 12