evmdm6437.h

DM643x Bootloader Flash烧写程序Flash=S29GL512N

#define MCASP1_SRCTL3           *( volatile Uint32* )( MCASP1_BASE + 0x18C )
#define MCASP1_XBUF0            *( volatile Uint32* )( MCASP1_BASE + 0x200 )
#define MCASP1_XBUF1            *( volatile Uint32* )( MCASP1_BASE + 0x204 )
#define MCASP1_XBUF2            *( volatile Uint32* )( MCASP1_BASE + 0x208 )
#define MCASP1_XBUF3            *( volatile Uint32* )( MCASP1_BASE + 0x20C )
#define MCASP1_RBUF0            *( volatile Uint32* )( MCASP1_BASE + 0x280 )
#define MCASP1_RBUF1            *( volatile Uint32* )( MCASP1_BASE + 0x284 )
#define MCASP1_RBUF2            *( volatile Uint32* )( MCASP1_BASE + 0x288 )
#define MCASP1_RBUF3            *( volatile Uint32* )( MCASP1_BASE + 0x28C )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  MCBSP Controller                                                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define MCBSP0_BASE             0x01D00000
#define MCBSP0_DRR_32BIT        *( volatile Uint32* )( MCBSP0_BASE + 0x00 )
#define MCBSP0_DRR_16BIT        *( volatile Uint16* )( MCBSP0_BASE + 0x00 )
#define MCBSP0_DXR_32BIT        *( volatile Uint32* )( MCBSP0_BASE + 0x04 )
#define MCBSP0_DXR_16BIT        *( volatile Uint16* )( MCBSP0_BASE + 0x04 )
#define MCBSP0_SPCR             *( volatile Uint32* )( MCBSP0_BASE + 0x08 )
#define MCBSP0_RCR              *( volatile Uint32* )( MCBSP0_BASE + 0x0C )
#define MCBSP0_XCR              *( volatile Uint32* )( MCBSP0_BASE + 0x10 )
#define MCBSP0_SRGR             *( volatile Uint32* )( MCBSP0_BASE + 0x14 )
#define MCBSP0_MCR              *( volatile Uint32* )( MCBSP0_BASE + 0x18 )
#define MCBSP0_PCR              *( volatile Uint32* )( MCBSP0_BASE + 0x24 )
#define MCBSP0_RCERE10          *( volatile Uint32* )( MCBSP0_BASE + 0x28 )
#define MCBSP0_XCERE10          *( volatile Uint32* )( MCBSP0_BASE + 0x2C )
#define MCBSP0_RCERE20          *( volatile Uint32* )( MCBSP0_BASE + 0x30 )
#define MCBSP0_XCERE20          *( volatile Uint32* )( MCBSP0_BASE + 0x34 )
#define MCBSP0_RCERE30          *( volatile Uint32* )( MCBSP0_BASE + 0x38 )
#define MCBSP0_XCERE30          *( volatile Uint32* )( MCBSP0_BASE + 0x3C )

#define MCBSP1_BASE             0x01D00800
#define MCBSP1_DRR_32BIT        *( volatile Uint32* )( MCBSP1_BASE + 0x00 )
#define MCBSP1_DRR_16BIT        *( volatile Uint16* )( MCBSP1_BASE + 0x00 )
#define MCBSP1_DXR_32BIT        *( volatile Uint32* )( MCBSP1_BASE + 0x04 )
#define MCBSP1_DXR_16BIT        *( volatile Uint16* )( MCBSP1_BASE + 0x04 )
#define MCBSP1_SPCR             *( volatile Uint32* )( MCBSP1_BASE + 0x08 )
#define MCBSP1_RCR              *( volatile Uint32* )( MCBSP1_BASE + 0x0C )
#define MCBSP1_XCR              *( volatile Uint32* )( MCBSP1_BASE + 0x10 )
#define MCBSP1_SRGR             *( volatile Uint32* )( MCBSP1_BASE + 0x14 )
#define MCBSP1_MCR              *( volatile Uint32* )( MCBSP1_BASE + 0x18 )
#define MCBSP1_PCR              *( volatile Uint32* )( MCBSP1_BASE + 0x24 )
#define MCBSP1_RCERE11          *( volatile Uint32* )( MCBSP1_BASE + 0x28 )
#define MCBSP1_XCERE11          *( volatile Uint32* )( MCBSP1_BASE + 0x2C )
#define MCBSP1_RCERE21          *( volatile Uint32* )( MCBSP1_BASE + 0x30 )
#define MCBSP1_XCERE21          *( volatile Uint32* )( MCBSP1_BASE + 0x34 )
#define MCBSP1_RCERE31          *( volatile Uint32* )( MCBSP1_BASE + 0x38 )
#define MCBSP1_XCERE31          *( volatile Uint32* )( MCBSP1_BASE + 0x3C )

#define MCBSP_SPCR_FREE                 0x02000000
#define MCBSP_SPCR_SOFT                 0x01000000
#define MCBSP_SPCR_FRST                 0x00800000
#define MCBSP_SPCR_GRST                 0x00400000
#define MCBSP_SPCR_XSYNCERR             0x00080000
#define MCBSP_SPCR_XEMPTY               0x00040000
#define MCBSP_SPCR_XRDY                 0x00020000
#define MCBSP_SPCR_XRST                 0x00010000
#define MCBSP_SPCR_DLB                  0x00008000
#define MCBSP_SPCR_DXENA                0x00000020
#define MCBSP_SPCR_ABIS                 0x00000010
#define MCBSP_SPCR_RSYNCERR             0x00000008
#define MCBSP_SPCR_RFULL                0x00000004
#define MCBSP_SPCR_RRDY                 0x00000002
#define MCBSP_SPCR_RRST                 0x00000001

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  MDIO Controller                                                         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define MDIO_BASE               0x01C84000
#define MDIO_VERSION            *( volatile Uint32* )( MDIO_BASE + 0x00 )
#define MDIO_CONTROL            *( volatile Uint32* )( MDIO_BASE + 0x04 )
#define MDIO_ALIVE              *( volatile Uint32* )( MDIO_BASE + 0x08 )
#define MDIO_LINK               *( volatile Uint32* )( MDIO_BASE + 0x0C )
#define MDIO_LINKINTRAW         *( volatile Uint32* )( MDIO_BASE + 0x10 )
#define MDIO_LINKINTMASKED      *( volatile Uint32* )( MDIO_BASE + 0x14 )
#define MDIO_USERINTRAW         *( volatile Uint32* )( MDIO_BASE + 0x20 )
#define MDIO_USERINTMASKED      *( volatile Uint32* )( MDIO_BASE + 0x24 )
#define MDIO_USERINTMASKSET     *( volatile Uint32* )( MDIO_BASE + 0x28 )
#define MDIO_USERINTMASKCLEAR   *( volatile Uint32* )( MDIO_BASE + 0x2C )
#define MDIO_USERACCESS0        *( volatile Uint32* )( MDIO_BASE + 0x80 )
#define MDIO_USERPHYSEL0        *( volatile Uint32* )( MDIO_BASE + 0x84 )
#define MDIO_USERACCESS1        *( volatile Uint32* )( MDIO_BASE + 0x88 )
#define MDIO_USERPHYSEL1        *( volatile Uint32* )( MDIO_BASE + 0x8C )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  PCI Control                                                             *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define PCI_BASE                0x01C1A000

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  PLL0 Controller                                                         *
 *      Generates DSP, DMA, VPFE clocks                                     *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define PLL0_BASE               0x01C40800
#define PLL0_PID                *( volatile Uint32* )( PLL0_BASE + 0x000 )
#define PLL0_RSTYPE             *( volatile Uint32* )( PLL0_BASE + 0x0E4 )
#define PLL0_PLLCTL             *( volatile Uint32* )( PLL0_BASE + 0x100 )
#define PLL0_PLLM               *( volatile Uint32* )( PLL0_BASE + 0x110 )
#define PLL0_PLLDIV1            *( volatile Uint32* )( PLL0_BASE + 0x118 )
#define PLL0_PLLDIV2            *( volatile Uint32* )( PLL0_BASE + 0x11C )
#define PLL0_PLLDIV3            *( volatile Uint32* )( PLL0_BASE + 0x120 )
#define PLL0_POSTDIV            *( volatile Uint32* )( PLL0_BASE + 0x128 )
#define PLL0_BPDIV              *( volatile Uint32* )( PLL0_BASE + 0x12C )
#define PLL0_CKEN               *( volatile Uint32* )( PLL0_BASE + 0x148 )
#define PLL0_CKSTAT             *( volatile Uint32* )( PLL0_BASE + 0x14C )
#define PLL0_SYSTAT             *( volatile Uint32* )( PLL0_BASE + 0x150 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  PLL1 Controller                                                         *
 *      Generates DDR2, VPBE clocks                                         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define PLL1_BASE               0x01C40C00
#define PLL1_PID                *( volatile Uint32* )( PLL1_BASE + 0x000 )
#define PLL1_PLLCTL             *( volatile Uint32* )( PLL1_BASE + 0x100 )
#define PLL1_PLLM               *( volatile Uint32* )( PLL1_BASE + 0x110 )
#define PLL1_PLLDIV1            *( volatile Uint32* )( PLL1_BASE + 0x118 )
#define PLL1_PLLDIV2            *( volatile Uint32* )( PLL1_BASE + 0x11C )
#define PLL1_PLLDIV3            *( volatile Uint32* )( PLL1_BASE + 0x120 )
#define PLL1_OSCDIV1            *( volatile Uint32* )( PLL1_BASE + 0x124 )
#define PLL1_POSTDIV            *( volatile Uint32* )( PLL1_BASE + 0x128 )
#define PLL1_BPDIV              *( volatile Uint32* )( PLL1_BASE + 0x12C )
#define PLL1_PLLCMD             *( volatile Uint32* )( PLL1_BASE + 0x138 )
#define PLL1_PLLSTAT            *( volatile Uint32* )( PLL1_BASE + 0x13C )
#define PLL1_ALNCTL             *( volatile Uint32* )( PLL1_BASE + 0x140 )
#define PLL1_DCHANGE            *( volatile Uint32* )( PLL1_BASE + 0x144 )
#define PLL1_CKEN               *( volatile Uint32* )( PLL1_BASE + 0x148 )
#define PLL1_CKSTAT             *( volatile Uint32* )( PLL1_BASE + 0x14C )
#define PLL1_SYSTAT             *( volatile Uint32* )( PLL1_BASE + 0x150 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  PSC ( Power and Sleep Controller )                                      *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define PSC_BASE                0x01C41000
#define PSC_GBLCTL              *( volatile Uint32* )( PSC_BASE + 0x010 )
#define PSC_INTEVAL             *( volatile Uint32* )( PSC_BASE + 0x018 )
#define PSC_MERRPR0             *( volatile Uint32* )( PSC_BASE + 0x040 )
#define PSC_MERRPR1             *( volatile Uint32* )( PSC_BASE + 0x044 )
#define PSC_MERRCR0             *( volatile Uint32* )( PSC_BASE + 0x050 )
#define PSC_MERRCR1             *( volatile Uint32* )( PSC_BASE + 0x054 )
#define PSC_PERRPR              *( volatile Uint32* )( PSC_BASE + 0x060 )
#define PSC_PERRCR              *( volatile Uint32* )( PSC_BASE + 0x068 )
#define PSC_PTCMD               *( volatile Uint32* )( PSC_BASE + 0x120 )
#define PSC_PTSTAT              *( volatile Uint32* )( PSC_BASE + 0x128 )
#define PSC_PDSTAT0             *( volatile Uint32* )( PSC_BASE + 0x200 )
#define PSC_PDCTL0              *( volatile Uint32* )( PSC_BASE + 0x300 )
#define PSC_MCKOUT0             *( volatile Uint32* )( PSC_BASE + 0x510 )
#define PSC_MCKOUT1             *( volatile Uint32* )( PSC_BASE + 0x514 )
#define PSC_MDSTAT_BASE         ( PSC_BASE + 0x800 )
#define PSC_MDCTL_BASE          ( PSC_BASE + 0xA00 )

#define LPSC_VPSS_DMA           0   // DM643x only
#define LPSC_VPSS_MMR           1   // DM643x only
#define LPSC_EDMACC             2
#define LPSC_EDMATC0            3
#define LPSC_EDMATC1            4
#define LPSC_EMACTC2            5
#define LPSC_EMAC_MEMORY        6
#define LPSC_MDIO               7
#define LPSC_EMAC               8
#define LPSC_MCASP0             9
#define LPSC_VLYNQ              11
#define LPSC_HPI                12
#define LPSC_DDR2               13
#define LPSC_EMIFA              14
#define LPSC_PCI                15
#define LPSC_MCBSP0             16
#define LPSC_MCBSP1             17
#define LPSC_I2C                18
#define LPSC_UART0              19
#define LPSC_UART1              20
#define LPSC_VPSS               21   // DM643x only
#define LPSC_HECC               22   // DM643x only
#define LPSC_PWM0               23
#define LPSC_PWM1               24
#define LPSC_PWM2               25
#define LPSC_GPIO               26
#define LPSC_TIMER0             27
#define LPSC_TIMER1             28
#define LPSC_C64X               39

/* ------------------------------------------------------------------------ *
 *