evmdm6437.h

DM643x Bootloader Flash烧写程序Flash=S29GL512N

#define HECC_RIOCE              *( volatile Uint32* )( HECC_BASE + 0x6C )
#define HECC_ETC                *( volatile Uint32* )( HECC_BASE + 0x70 )

#define HECC_RAM_BASE           0x01C24000
#define HECC_MBX_0              *( volatile Uint32* )( HECC_RAM_BASE + 0x00 )
#define HECC_MBX_1              *( volatile Uint32* )( HECC_RAM_BASE + 0x04 )
#define HECC_MBX_2              *( volatile Uint32* )( HECC_RAM_BASE + 0x08 )
#define HECC_MBX_3              *( volatile Uint32* )( HECC_RAM_BASE + 0x0C )
#define HECC_MBX_4              *( volatile Uint32* )( HECC_RAM_BASE + 0x10 )
#define HECC_MBX_5              *( volatile Uint32* )( HECC_RAM_BASE + 0x14 )
#define HECC_MBX_6              *( volatile Uint32* )( HECC_RAM_BASE + 0x18 )
#define HECC_MBX_7              *( volatile Uint32* )( HECC_RAM_BASE + 0x1C )
#define HECC_MBX_8              *( volatile Uint32* )( HECC_RAM_BASE + 0x20 )
#define HECC_MBX_9              *( volatile Uint32* )( HECC_RAM_BASE + 0x24 )
#define HECC_MBX_10             *( volatile Uint32* )( HECC_RAM_BASE + 0x28 )
#define HECC_MBX_11             *( volatile Uint32* )( HECC_RAM_BASE + 0x2C )
#define HECC_MBX_12             *( volatile Uint32* )( HECC_RAM_BASE + 0x30 )
#define HECC_MBX_13             *( volatile Uint32* )( HECC_RAM_BASE + 0x34 )
#define HECC_MBX_14             *( volatile Uint32* )( HECC_RAM_BASE + 0x38 )
#define HECC_MBX_15             *( volatile Uint32* )( HECC_RAM_BASE + 0x3C )
#define HECC_MBX_16             *( volatile Uint32* )( HECC_RAM_BASE + 0x40 )
#define HECC_MBX_17             *( volatile Uint32* )( HECC_RAM_BASE + 0x44 )
#define HECC_MBX_18             *( volatile Uint32* )( HECC_RAM_BASE + 0x48 )
#define HECC_MBX_19             *( volatile Uint32* )( HECC_RAM_BASE + 0x4C )
#define HECC_MBX_20             *( volatile Uint32* )( HECC_RAM_BASE + 0x50 )
#define HECC_MBX_21             *( volatile Uint32* )( HECC_RAM_BASE + 0x54 )
#define HECC_MBX_22             *( volatile Uint32* )( HECC_RAM_BASE + 0x58 )
#define HECC_MBX_23             *( volatile Uint32* )( HECC_RAM_BASE + 0x5C )
#define HECC_MBX_24             *( volatile Uint32* )( HECC_RAM_BASE + 0x60 )
#define HECC_MBX_25             *( volatile Uint32* )( HECC_RAM_BASE + 0x64 )
#define HECC_MBX_26             *( volatile Uint32* )( HECC_RAM_BASE + 0x68 )
#define HECC_MBX_27             *( volatile Uint32* )( HECC_RAM_BASE + 0x6C )
#define HECC_MBX_28             *( volatile Uint32* )( HECC_RAM_BASE + 0x70 )
#define HECC_MBX_29             *( volatile Uint32* )( HECC_RAM_BASE + 0x74 )
#define HECC_MBX_30             *( volatile Uint32* )( HECC_RAM_BASE + 0x78 )
#define HECC_MBX_31             *( volatile Uint32* )( HECC_RAM_BASE + 0x7C )

#define HECC_LAM_0              *( volatile Uint32* )( HECC_RAM_BASE + 0xE80 )
#define HECC_LAM_1              *( volatile Uint32* )( HECC_RAM_BASE + 0xE84 )
#define HECC_LAM_2              *( volatile Uint32* )( HECC_RAM_BASE + 0xE88 )
#define HECC_LAM_3              *( volatile Uint32* )( HECC_RAM_BASE + 0xE8C )
#define HECC_LAM_4              *( volatile Uint32* )( HECC_RAM_BASE + 0xE90 )
#define HECC_LAM_5              *( volatile Uint32* )( HECC_RAM_BASE + 0xE94 )
#define HECC_LAM_6              *( volatile Uint32* )( HECC_RAM_BASE + 0xE98 )
#define HECC_LAM_7              *( volatile Uint32* )( HECC_RAM_BASE + 0xE9C )
#define HECC_LAM_8              *( volatile Uint32* )( HECC_RAM_BASE + 0xEA0 )
#define HECC_LAM_9              *( volatile Uint32* )( HECC_RAM_BASE + 0xEA4 )
#define HECC_LAM_10             *( volatile Uint32* )( HECC_RAM_BASE + 0xEA8 )
#define HECC_LAM_11             *( volatile Uint32* )( HECC_RAM_BASE + 0xEAC )
#define HECC_LAM_12             *( volatile Uint32* )( HECC_RAM_BASE + 0xEB0 )
#define HECC_LAM_13             *( volatile Uint32* )( HECC_RAM_BASE + 0xEB4 )
#define HECC_LAM_14             *( volatile Uint32* )( HECC_RAM_BASE + 0xEB8 )
#define HECC_LAM_15             *( volatile Uint32* )( HECC_RAM_BASE + 0xEBC )
#define HECC_LAM_16             *( volatile Uint32* )( HECC_RAM_BASE + 0xEC0 )
#define HECC_LAM_17             *( volatile Uint32* )( HECC_RAM_BASE + 0xEC4 )
#define HECC_LAM_18             *( volatile Uint32* )( HECC_RAM_BASE + 0xEC8 )
#define HECC_LAM_19             *( volatile Uint32* )( HECC_RAM_BASE + 0xECC )
#define HECC_LAM_20             *( volatile Uint32* )( HECC_RAM_BASE + 0xED0 )
#define HECC_LAM_21             *( volatile Uint32* )( HECC_RAM_BASE + 0xED4 )
#define HECC_LAM_22             *( volatile Uint32* )( HECC_RAM_BASE + 0xED8 )
#define HECC_LAM_23             *( volatile Uint32* )( HECC_RAM_BASE + 0xEDC )
#define HECC_LAM_24             *( volatile Uint32* )( HECC_RAM_BASE + 0xEE0 )
#define HECC_LAM_25             *( volatile Uint32* )( HECC_RAM_BASE + 0xEE4 )
#define HECC_LAM_26             *( volatile Uint32* )( HECC_RAM_BASE + 0xEE8 )
#define HECC_LAM_27             *( volatile Uint32* )( HECC_RAM_BASE + 0xEEC )
#define HECC_LAM_28             *( volatile Uint32* )( HECC_RAM_BASE + 0xEF0 )
#define HECC_LAM_29             *( volatile Uint32* )( HECC_RAM_BASE + 0xEF4 )
#define HECC_LAM_30             *( volatile Uint32* )( HECC_RAM_BASE + 0xEF8 )
#define HECC_LAM_31             *( volatile Uint32* )( HECC_RAM_BASE + 0xEFC )

#define HECC_MOTS_0             *( volatile Uint32* )( HECC_RAM_BASE + 0xF00 )
#define HECC_MOTS_1             *( volatile Uint32* )( HECC_RAM_BASE + 0xF04 )
#define HECC_MOTS_2             *( volatile Uint32* )( HECC_RAM_BASE + 0xF08 )
#define HECC_MOTS_3             *( volatile Uint32* )( HECC_RAM_BASE + 0xF0C )
#define HECC_MOTS_4             *( volatile Uint32* )( HECC_RAM_BASE + 0xF10 )
#define HECC_MOTS_5             *( volatile Uint32* )( HECC_RAM_BASE + 0xF14 )
#define HECC_MOTS_6             *( volatile Uint32* )( HECC_RAM_BASE + 0xF18 )
#define HECC_MOTS_7             *( volatile Uint32* )( HECC_RAM_BASE + 0xF1C )
#define HECC_MOTS_8             *( volatile Uint32* )( HECC_RAM_BASE + 0xF20 )
#define HECC_MOTS_9             *( volatile Uint32* )( HECC_RAM_BASE + 0xF24 )
#define HECC_MOTS_10            *( volatile Uint32* )( HECC_RAM_BASE + 0xF28 )
#define HECC_MOTS_11            *( volatile Uint32* )( HECC_RAM_BASE + 0xF2C )
#define HECC_MOTS_12            *( volatile Uint32* )( HECC_RAM_BASE + 0xF30 )
#define HECC_MOTS_13            *( volatile Uint32* )( HECC_RAM_BASE + 0xF34 )
#define HECC_MOTS_14            *( volatile Uint32* )( HECC_RAM_BASE + 0xF38 )
#define HECC_MOTS_15            *( volatile Uint32* )( HECC_RAM_BASE + 0xF3C )
#define HECC_MOTS_16            *( volatile Uint32* )( HECC_RAM_BASE + 0xF40 )
#define HECC_MOTS_17            *( volatile Uint32* )( HECC_RAM_BASE + 0xF44 )
#define HECC_MOTS_18            *( volatile Uint32* )( HECC_RAM_BASE + 0xF48 )
#define HECC_MOTS_19            *( volatile Uint32* )( HECC_RAM_BASE + 0xF4C )
#define HECC_MOTS_20            *( volatile Uint32* )( HECC_RAM_BASE + 0xF50 )
#define HECC_MOTS_21            *( volatile Uint32* )( HECC_RAM_BASE + 0xF54 )
#define HECC_MOTS_22            *( volatile Uint32* )( HECC_RAM_BASE + 0xF58 )
#define HECC_MOTS_23            *( volatile Uint32* )( HECC_RAM_BASE + 0xF5C )
#define HECC_MOTS_24            *( volatile Uint32* )( HECC_RAM_BASE + 0xF60 )
#define HECC_MOTS_25            *( volatile Uint32* )( HECC_RAM_BASE + 0xF64 )
#define HECC_MOTS_26            *( volatile Uint32* )( HECC_RAM_BASE + 0xF68 )
#define HECC_MOTS_27            *( volatile Uint32* )( HECC_RAM_BASE + 0xF6C )
#define HECC_MOTS_28            *( volatile Uint32* )( HECC_RAM_BASE + 0xF70 )
#define HECC_MOTS_29            *( volatile Uint32* )( HECC_RAM_BASE + 0xF74 )
#define HECC_MOTS_30            *( volatile Uint32* )( HECC_RAM_BASE + 0xF78 )
#define HECC_MOTS_31            *( volatile Uint32* )( HECC_RAM_BASE + 0xF7C )

#define HECC_MOTO_0             *( volatile Uint32* )( HECC_RAM_BASE + 0xF80 )
#define HECC_MOTO_1             *( volatile Uint32* )( HECC_RAM_BASE + 0xF84 )
#define HECC_MOTO_2             *( volatile Uint32* )( HECC_RAM_BASE + 0xF88 )
#define HECC_MOTO_3             *( volatile Uint32* )( HECC_RAM_BASE + 0xF8C )
#define HECC_MOTO_4             *( volatile Uint32* )( HECC_RAM_BASE + 0xF90 )
#define HECC_MOTO_5             *( volatile Uint32* )( HECC_RAM_BASE + 0xF94 )
#define HECC_MOTO_6             *( volatile Uint32* )( HECC_RAM_BASE + 0xF98 )
#define HECC_MOTO_7             *( volatile Uint32* )( HECC_RAM_BASE + 0xF9C )
#define HECC_MOTO_8             *( volatile Uint32* )( HECC_RAM_BASE + 0xFA0 )
#define HECC_MOTO_9             *( volatile Uint32* )( HECC_RAM_BASE + 0xFA4 )
#define HECC_MOTO_10            *( volatile Uint32* )( HECC_RAM_BASE + 0xFA8 )
#define HECC_MOTO_11            *( volatile Uint32* )( HECC_RAM_BASE + 0xFAC )
#define HECC_MOTO_12            *( volatile Uint32* )( HECC_RAM_BASE + 0xFB0 )
#define HECC_MOTO_13            *( volatile Uint32* )( HECC_RAM_BASE + 0xFB4 )
#define HECC_MOTO_14            *( volatile Uint32* )( HECC_RAM_BASE + 0xFB8 )
#define HECC_MOTO_15            *( volatile Uint32* )( HECC_RAM_BASE + 0xFBC )
#define HECC_MOTO_16            *( volatile Uint32* )( HECC_RAM_BASE + 0xFC0 )
#define HECC_MOTO_17            *( volatile Uint32* )( HECC_RAM_BASE + 0xFC4 )
#define HECC_MOTO_18            *( volatile Uint32* )( HECC_RAM_BASE + 0xFC8 )
#define HECC_MOTO_19            *( volatile Uint32* )( HECC_RAM_BASE + 0xFCC )
#define HECC_MOTO_20            *( volatile Uint32* )( HECC_RAM_BASE + 0xFD0 )
#define HECC_MOTO_21            *( volatile Uint32* )( HECC_RAM_BASE + 0xFD4 )
#define HECC_MOTO_22            *( volatile Uint32* )( HECC_RAM_BASE + 0xFD8 )
#define HECC_MOTO_23            *( volatile Uint32* )( HECC_RAM_BASE + 0xFDC )
#define HECC_MOTO_24            *( volatile Uint32* )( HECC_RAM_BASE + 0xFE0 )
#define HECC_MOTO_25            *( volatile Uint32* )( HECC_RAM_BASE + 0xFE4 )
#define HECC_MOTO_26            *( volatile Uint32* )( HECC_RAM_BASE + 0xFE8 )
#define HECC_MOTO_27            *( volatile Uint32* )( HECC_RAM_BASE + 0xFEC )
#define HECC_MOTO_28            *( volatile Uint32* )( HECC_RAM_BASE + 0xFF0 )
#define HECC_MOTO_29            *( volatile Uint32* )( HECC_RAM_BASE + 0xFF4 )
#define HECC_MOTO_30            *( volatile Uint32* )( HECC_RAM_BASE + 0xFF8 )
#define HECC_MOTO_31            *( volatile Uint32* )( HECC_RAM_BASE + 0xFFC )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  HPI Controller                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define HPI_BASE                0x01C67800
#define HPI_PWREMU_MGMT         *( volatile Uint32* )( HPI_BASE + 0x04 )
#define HPI_HPIC                *( volatile Uint32* )( HPI_BASE + 0x30 )
#define HPI_HPIAW               *( volatile Uint32* )( HPI_BASE + 0x34 )
#define HPI_HPIAR               *( volatile Uint32* )( HPI_BASE + 0x08 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  I2C Controller                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define I2C_BASE                0x01C21000
#define I2C_OAR                 *( volatile Uint32* )( I2C_BASE + 0x00 )
#define I2C_ICIMR               *( volatile Uint32* )( I2C_BASE + 0x04 )
#define I2C_ICSTR               *( volatile Uint32* )( I2C_BASE + 0x08 )
#define I2C_ICCLKL              *( volatile Uint32* )( I2C_BASE + 0x0C )
#define I2C_ICCLKH              *( volatile Uint32* )( I2C_BASE + 0x10 )
#define I2C_ICCNT               *( volatile Uint32* )( I2C_BASE + 0x14 )
#define I2C_ICDRR               *( volatile Uint32* )( I2C_BASE + 0x18 )
#define I2C_ICSAR               *( volatile Uint32* )( I2C_BASE + 0x1C )
#define I2C_ICDXR               *( volatile Uint32* )( I2C_BASE + 0x20 )
#define I2C_ICMDR               *( volatile Uint32* )( I2C_BASE + 0x24 )
#define I2C_ICIVR               *( volatile Uint32* )( I2C_BASE + 0x28 )
#define I2C_ICEMDR              *( volatile Uint32* )( I2C_BASE + 0x2C )
#define I2C_ICPSC               *( volatile Uint32* )( I2C_BASE + 0x30 )
#define I2C_ICPID1              *( volatile Uint32* )( I2C_BASE + 0x34 )
#define I2C_ICPID2              *( volatile Uint32* )( I2C_BASE + 0x38 )

/* I2C Field Definitions */
#define ICOAR_MASK_7                    0x007F
#define ICOAR_MASK_10                   0x03FF
#define ICSAR_MASK_7                    0x007F
#define ICSAR_MASK_10                   0x03FF
#define ICOAR_OADDR                     0x007f
#define ICSAR_SADDR                     0x0050

#define ICSTR_SDIR                      0x4000
#define ICSTR_NACKINT                   0x2000
#define ICSTR_BB                        0x1000
#define ICSTR_RSFULL                    0x0800
#define ICSTR_XSMT                      0x0400
#define ICSTR_AAS                       0x0200
#define ICSTR_AD0                       0x0100
#define ICSTR_SCD                       0x0020
#define ICSTR_ICXRDY                    0x0010
#define ICSTR_ICRRDY                    0x0008
#define ICSTR_ARDY                      0x0004
#define ICSTR_NACK                      0x0002
#define ICSTR_AL                        0x0001

#define ICMDR_NACKMOD                   0x8000
#define ICMDR_FREE                      0x4000
#define ICMDR_STT                       0x2000
#define ICMDR_IDLEEN                    0x1000