evmdm6437.h

DM643x Bootloader Flash烧写程序Flash=S29GL512N

/*
 *  Copyright 2006 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 *
 *  Not for distribution.
 */

/*
 *  Definitions & Register
 *
 */

#ifndef EVMDM6437_
#define EVMDM6437_

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Variable types                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define Uint32  unsigned int
#define Uint16  unsigned short
#define Uint8   unsigned char
#define Int32   int
#define Int16   short
#define Int8    char

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Software Breakpoint code                                                *
 *      Uses inline assembly command                                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define SW_BREAKPOINT           asm( " .long 0x1001E000" );

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  AEMIF Controller                                                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define AEMIF_BASE              0x01E00000
#define AEMIF_AWCCR             *( volatile Uint32* )( AEMIF_BASE + 0x04 )
#define AEMIF_A1CR              *( volatile Uint32* )( AEMIF_BASE + 0x10 )
#define AEMIF_A2CR              *( volatile Uint32* )( AEMIF_BASE + 0x14 )
#define AEMIF_A3CR              *( volatile Uint32* )( AEMIF_BASE + 0x18 )
#define AEMIF_A4CR              *( volatile Uint32* )( AEMIF_BASE + 0x1C )
#define AEMIF_EIRR              *( volatile Uint32* )( AEMIF_BASE + 0x40 )
#define AEMIF_EIMR              *( volatile Uint32* )( AEMIF_BASE + 0x44 )
#define AEMIF_EMISR             *( volatile Uint32* )( AEMIF_BASE + 0x48 )
#define AEMIF_EIMCR             *( volatile Uint32* )( AEMIF_BASE + 0x4C )
#define AEMIF_NANDFCR           *( volatile Uint32* )( AEMIF_BASE + 0x60 )
#define AEMIF_NANDFSR           *( volatile Uint32* )( AEMIF_BASE + 0x64 )
#define AEMIF_NANDECC2          *( volatile Uint32* )( AEMIF_BASE + 0x70 )
#define AEMIF_NANDECC3          *( volatile Uint32* )( AEMIF_BASE + 0x74 )
#define AEMIF_NANDECC4          *( volatile Uint32* )( AEMIF_BASE + 0x78 )
#define AEMIF_NANDECC5          *( volatile Uint32* )( AEMIF_BASE + 0x7C )

#define AEMIF_MAX_TIMEOUT_8BIT  0x3FFFFFFC
#define AEMIF_MAX_TIMEOUT_16BIT 0x3FFFFFFD

#define EMIF_CS2                2
#define EMIF_CS3                3
#define EMIF_CS4                4
#define EMIF_CS5                5

#define EMIF_CS2_BASE           0x42000000
#define EMIF_CS3_BASE           0x44000000
#define EMIF_CS4_BASE           0x46000000
#define EMIF_CS5_BASE           0x48000000

#define EMIF_NAND_MODE          1
#define EMIF_NORMAL_MODE        0

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Device Config Controller                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define DEV_CFG_BASE            0x01C40000
#define CFG_PINMUX0             *( volatile Uint32* )( DEV_CFG_BASE + 0x00 )
#define CFG_PINMUX1             *( volatile Uint32* )( DEV_CFG_BASE + 0x04 )
#define CFG_DSPBOOTADDR         *( volatile Uint32* )( DEV_CFG_BASE + 0x08 )
#define CFG_SUSPSRC             *( volatile Uint32* )( DEV_CFG_BASE + 0x0C )
#define CFG_BOOTCFG             *( volatile Uint32* )( DEV_CFG_BASE + 0x14 )
#define CFG_DEVICE_ID           *( volatile Uint32* )( DEV_CFG_BASE + 0x28 )
#define CFG_UHPICTL             *( volatile Uint32* )( DEV_CFG_BASE + 0x30 )
#define CFG_MSTPRI0             *( volatile Uint32* )( DEV_CFG_BASE + 0x3C )
#define CFG_MSTPRI1             *( volatile Uint32* )( DEV_CFG_BASE + 0x40 )
#define CFG_VPSS_CLKCTL         *( volatile Uint32* )( DEV_CFG_BASE + 0x44 )// DM643x only
#define CFG_VDD3P3V_PWDN        *( volatile Uint32* )( DEV_CFG_BASE + 0x48 )
#define CFG_TIMERCTL            *( volatile Uint32* )( DEV_CFG_BASE + 0x84 )
#define CFG_TPTCCCFG            *( volatile Uint32* )( DEV_CFG_BASE + 0x88 )
#define CFG_RSTYPE              *( volatile Uint32* )( DEV_CFG_BASE + 0xE4 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DDR Controller                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define DDR_BASE                0x20000000
#define DDR_DDRVTPER            *( volatile Uint32* )( 0x01C4004C )
#define DDR_DDRVTPR             *( volatile Uint32* )( 0x01C42038 )
#define DDR_SDRSTAT             *( volatile Uint32* )( DDR_BASE + 0x04 )
#define DDR_SDBCR               *( volatile Uint32* )( DDR_BASE + 0x08 )
#define DDR_SDRCR               *( volatile Uint32* )( DDR_BASE + 0x0C )
#define DDR_SDTIMR              *( volatile Uint32* )( DDR_BASE + 0x10 )
#define DDR_SDTIMR2             *( volatile Uint32* )( DDR_BASE + 0x14 )
#define DDR_PBBPR               *( volatile Uint32* )( DDR_BASE + 0x20 )
#define DDR_IRR                 *( volatile Uint32* )( DDR_BASE + 0xC0 )
#define DDR_IMR                 *( volatile Uint32* )( DDR_BASE + 0xC4 )
#define DDR_IMSR                *( volatile Uint32* )( DDR_BASE + 0xC8 )
#define DDR_IMCR                *( volatile Uint32* )( DDR_BASE + 0xCC )
#define DDR_DDRPHYCR            *( volatile Uint32* )( DDR_BASE + 0xE4 )
#define DDR_VTPIOCR             *( volatile Uint32* )( DDR_BASE + 0xF0 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  EDMA Controller                                                         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define EDMA_BASE               0x01C00000
#define EDMA_CCCFG              *( volatile Uint32* )( EDMA_BASE + 0x04 )

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  EMAC controller                                                         *
 *      Controls the EMAC                                                   *
 *                                                                          *
 * ------------------------------------------------------------------------ */
#define EMAC_BASE               0x01C80000
#define EMAC_TXIDVER            *( volatile Uint32* )( EMAC_BASE + 0x000 )
#define EMAC_TXCONTROL          *( volatile Uint32* )( EMAC_BASE + 0x004 )
#define EMAC_TXTEARDOWN         *( volatile Uint32* )( EMAC_BASE + 0x008 )
#define EMAC_RXIDVER            *( volatile Uint32* )( EMAC_BASE + 0x010 )
#define EMAC_RXCONTROL          *( volatile Uint32* )( EMAC_BASE + 0x014 )
#define EMAC_RXTEARDOWN         *( volatile Uint32* )( EMAC_BASE + 0x018 )
#define EMAC_TXINTSTATRAW       *( volatile Uint32* )( EMAC_BASE + 0x080 )
#define EMAC_TXINTSTATMASKED    *( volatile Uint32* )( EMAC_BASE + 0x084 )
#define EMAC_TXINTMASKSET       *( volatile Uint32* )( EMAC_BASE + 0x088 )
#define EMAC_TXINTMASKCLEAR     *( volatile Uint32* )( EMAC_BASE + 0x08C )
#define EMAC_MACINVECTOR        *( volatile Uint32* )( EMAC_BASE + 0x090 )
#define EMAC_RXINTSTATRAW       *( volatile Uint32* )( EMAC_BASE + 0x0A0 )
#define EMAC_RXINTSTATMASKED    *( volatile Uint32* )( EMAC_BASE + 0x0A4 )
#define EMAC_RXINTMASKSET       *( volatile Uint32* )( EMAC_BASE + 0x0A8 )
#define EMAC_RXINTMASKCLEAR     *( volatile Uint32* )( EMAC_BASE + 0x0AC )
#define EMAC_MACINTSTATRAW      *( volatile Uint32* )( EMAC_BASE + 0x0B0 )
#define EMAC_MACINTSTATMASKED   *( volatile Uint32* )( EMAC_BASE + 0x0B4 )
#define EMAC_MACINTMASKSET      *( volatile Uint32* )( EMAC_BASE + 0x0B8 )
#define EMAC_MACINTMASKCLEAR    *( volatile Uint32* )( EMAC_BASE + 0x0BC )
#define EMAC_RXMBPENABLE        *( volatile Uint32* )( EMAC_BASE + 0x100 )
#define EMAC_RXUNICASTSET       *( volatile Uint32* )( EMAC_BASE + 0x104 )
#define EMAC_RXUNICASTCLEAR     *( volatile Uint32* )( EMAC_BASE + 0x108 )
#define EMAC_RXMAXLEN           *( volatile Uint32* )( EMAC_BASE + 0x10C )
#define EMAC_RXBUFFEROFFSET     *( volatile Uint32* )( EMAC_BASE + 0x110 )
#define EMAC_RXFILTERLOWTHRESH  *( volatile Uint32* )( EMAC_BASE + 0x114 )
#define EMAC_RX0FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x120 )
#define EMAC_RX1FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x124 )
#define EMAC_RX2FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x128 )
#define EMAC_RX3FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x12C )
#define EMAC_RX4FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x130 )
#define EMAC_RX5FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x134 )
#define EMAC_RX6FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x138 )
#define EMAC_RX7FLOWTHRESH      *( volatile Uint32* )( EMAC_BASE + 0x13C )
#define EMAC_RX0FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x140 )
#define EMAC_RX1FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x144 )
#define EMAC_RX2FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x148 )
#define EMAC_RX3FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x14C )
#define EMAC_RX4FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x150 )
#define EMAC_RX5FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x154 )
#define EMAC_RX6FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x158 )
#define EMAC_RX7FREEBUFFER      *( volatile Uint32* )( EMAC_BASE + 0x15C )
#define EMAC_MACCONTROL         *( volatile Uint32* )( EMAC_BASE + 0x160 )
#define EMAC_MACSTATUS          *( volatile Uint32* )( EMAC_BASE + 0x164 )
#define EMAC_EMCONTROL          *( volatile Uint32* )( EMAC_BASE + 0x168 )
#define EMAC_FIFOCONTROL        *( volatile Uint32* )( EMAC_BASE + 0x16C )
#define EMAC_MACCONFIG          *( volatile Uint32* )( EMAC_BASE + 0x170 )
#define EMAC_SOFTRESET          *( volatile Uint32* )( EMAC_BASE + 0x174 )
#define EMAC_MACSRCADDRLO       *( volatile Uint32* )( EMAC_BASE + 0x1D0 )
#define EMAC_MACSRCADDRHI       *( volatile Uint32* )( EMAC_BASE + 0x1D4 )
#define EMAC_MACHASH1           *( volatile Uint32* )( EMAC_BASE + 0x1D8 )
#define EMAC_MACHASH2           *( volatile Uint32* )( EMAC_BASE + 0x1DC )
#define EMAC_BOFFTEST           *( volatile Uint32* )( EMAC_BASE + 0x001 )
#define EMAC_TPACETEST          *( volatile Uint32* )( EMAC_BASE + 0x1E4 )
#define EMAC_RXPAUSE            *( volatile Uint32* )( EMAC_BASE + 0x1E8 )
#define EMAC_TXPAUSE            *( volatile Uint32* )( EMAC_BASE + 0x1EC )
#define EMAC_MACADDRLO          *( volatile Uint32* )( EMAC_BASE + 0x500 )
#define EMAC_MACADDRHI          *( volatile Uint32* )( EMAC_BASE + 0x504 )
#define EMAC_MACINDEX           *( volatile Uint32* )( EMAC_BASE + 0x508 )
#define EMAC_TX0HDP             *( volatile Uint32* )( EMAC_BASE + 0x600 )
#define EMAC_TX1HDP             *( volatile Uint32* )( EMAC_BASE + 0x604 )
#define EMAC_TX2HDP             *( volatile Uint32* )( EMAC_BASE + 0x608 )
#define EMAC_TX3HDP             *( volatile Uint32* )( EMAC_BASE + 0x60C )
#define EMAC_TX4HDP             *( volatile Uint32* )( EMAC_BASE + 0x610 )
#define EMAC_TX5HDP             *( volatile Uint32* )( EMAC_BASE + 0x614 )
#define EMAC_TX6HDP             *( volatile Uint32* )( EMAC_BASE + 0x618 )