bufg_phase_clk2x_subm.v

来自「本示例中使用了一个DCM模块」· Verilog 代码 · 共 91 行

//
// Module:      BUFG_PHASE_CLK2X_SUBM
//
// Description: Verilog Submodule
//  DCM with CLK2X deskew with the fine phase adjustment feature in
//    VARIABLE mode. 
//  
// Device:  Spartan-3 Family 
//
//---------------------------------------------------------------------

module BUFG_PHASE_CLK2X_SUBM (
                              CLK_IN,
                              RST,
                              PSEN,
                              PSINCDEC,
                              CLK2X,
                              LOCK,
                              PSDONE
                             );

    input CLK_IN;
    input RST;
    input PSEN;
    input PSINCDEC;

    output CLK2X;
    output LOCK;
    output PSDONE;

    wire CLK2X_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation//
    BUFG U0_BUFG (  
                  .I(CLK2X_W),
                  .O(CLK2X)
                 );
    
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.DLL_FREQUENCY_MODE = "HIGH";
       defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
       defparam U_DCM.CLKOUT_PHASE_SHIFT = "VARIABLE";
       defparam U_DCM.PHASE_SHIFT = 0;
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    // DCM Instantiation for the VARIABLE mode.
       DCM U_DCM ( 
                  .CLKFB(CLK2X), 
                  .CLKIN(CLK_IN), 
                  .DSSEN(GND), 
                  .PSCLK(CLK_IN), 
                  .PSEN(PSEN), 
                  .PSINCDEC(PSINCDEC), 
                  .RST(RST), 
                  .CLK2X(CLK2X_W), 
                  .LOCKED(LOCK), 
                  .PSDONE(PSDONE)
                 );

   /* DCM Instantiation for the FIXED mode.Note that the PSCLK,PSEN,PSINCDEC signals
   are tied to Ground. The PSEN,PSINCDEC,PSDONE signals have to be removed from the
   module declaration and port list.
     DCM U_DCM ( 
                .CLKFB(CLK2X), 
                .CLKIN(CLK_IN), 
                .DSSEN(GND), 
                .PSCLK(GND), 
                .PSEN(GND), 
                .PSINCDEC(GND), 
                .RST(RST), 
                .CLK2X(CLK2X_W), 
                .LOCKED(LOCK)
               ); */
    
   // synthesis attribute declarations
     /* synopsys attribute 
   
     DLL_FREQUENCY_MODE "HIGH"
     DUTY_CYCLE_CORRECTION "TRUE"
     CLKOUT_PHASE_SHIFT "VARIABLE"
     PHASE_SHIFT "0"
     STARTUP_WAIT "FALSE"
     */
endmodule