bufg_phase_clkfx_fb_subm.v

本示例中使用了一个DCM模块

//
// Module:      BUFG_PHASE_CLKFX_FB_SUBM
//
// Description: Verilog Submodule
//		DCM with CLKFX deskew and in phase with CLK_IN.
//    The fine phase adjustment feature is in VARIABLE mode. 
//		
// Device: 	Spartan-3 Family 
//
//---------------------------------------------------------------------

module BUFG_PHASE_CLKFX_FB_SUBM (
                                 CLK_IN, 
                                 RST,
                                 CLK1X,
                                 CLKFX,
                                 CLKFX180,
                                 PSEN,
                                 PSINCDEC,
                                 LOCK,
                                 PSDONE
                                );

    input CLK_IN;
    input RST;
    input PSEN;
    input PSINCDEC;

    output CLK1X;
    output CLKFX;
    output CLKFX180;
    output LOCK;
    output PSDONE;

    wire CLKFX_W;
    wire CLKFX180_W;
    wire CLK0_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation for CLK0//
    BUFG U0_BUFG (  
                  .I(CLK0_W),
                  .O(CLK1X)
                 );

    // BUFG Instantiation for CLKFX//
    BUFG U1_BUFG (  
                  .I(CLKFX_W),
                  .O(CLKFX)
                 );

    // BUFG Instantiation for CLKFX180//
    BUFG U2_BUFG (  
                  .I(CLKFX180_W),
                  .O(CLKFX180)
                 );
 	 
    // Attributes for functional simulation//
    // synopsys translate_off
    defparam U_DCM.DFS_FREQUENCY_MODE = "LOW";
    defparam U_DCM.CLKFX_DIVIDE = 1;
    defparam U_DCM.CLKFX_MULTIPLY = 4;
    defparam U_DCM.CLKOUT_PHASE_SHIFT = "VARIABLE";
    defparam U_DCM.PHASE_SHIFT = 0;
    defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
    defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    // DCM Instantiation for the VARIABLE mode.
    DCM U_DCM ( 
               .CLKIN(CLK_IN), 
               .CLKFB(CLK1X), 
               .DSSEN(GND), 
               .PSCLK(CLK_IN), 
               .PSEN(PSEN), 
               .PSINCDEC(PSINCDEC), 
               .RST(RST), 
               .CLK0(CLK0_W), 
               .CLKFX(CLKFX_W), 
               .CLKFX180(CLKFX180_W), 
               .LOCKED(LOCK), 
               .PSDONE(PSDONE)
              );
 
    /* DCM Instantiation for the FIXED mode.Note that the PSCLK,PSEN,PSINCDEC signals
    are tied to Ground. The PSEN,PSINCDEC,PSDONE signals have to be removed from the
    module declaration and port list.
    DCM U_DCM ( 
                .CLKIN(CLK_IN), 
                .CLKFB(CLK1X), 
                .DSSEN(GND), 
                .PSCLK(GND), 
                .PSEN(GND), 
                .PSINCDEC(GND), 
                .RST(RST), 
                .CLK0(CLK0_W),
                .CLKFX(CLKFX_W), 
                .CLKFX180(CLKFX180_W),
	        .LOCKED(LOCK)
               ); */
				 		             
   // synthesis attribute declarations
     /* synopsys attribute
 
     DFS_FREQUENCY_MODE "LOW"
     CLKFX_DIVIDE "1"
     CLKFX_MULTIPLY "4"
     CLKOUT_PHASE_SHIFT "VARIABLE"
     PHASE_SHIFT "0"
     DUTY_CYCLE_CORRECTION "TRUE"
     STARTUP_WAIT "FALSE"
     */
endmodule