readme_dcm_verilog.txt

来自「本示例中使用了一个DCM模块」· 文本 代码 · 共 42 行

README file: XAPP462 - Using DCMs in Spartan-3 FPGAs
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Date: July, 2003

Verilog code examples are provided to illustrate XAPP462 - Using DCMs in Spartan-3 FPGAs

- Verilog Templates:
Verilog templates are available as examples to instantiate primitives. 

- Verilog Submodules:
Verilog submodules are low level Verilog code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

Templates (primitive):
 DCM_INST

Submodules (code example):
 
 - Clock de-skew
 BUFG_CLK0_SUBM
 BUFG_CLK2X_SUBM
 BUFG_CLK0_FB_SUBM
 BUFG_CLK2X_FB_SUBM
 BUFG_CLKDV_SUBM
 
 - Frequency synthesizer
 BUFG_DFS_SUBM
 BUFG_DFS_FB_SUBM

 - Phase shifter
 BUFG_PHASE_CLKFX_FB_SUBM
 BUFG_PHASE_CLK0_SUBM
 BUFG_PHASE_CLK2X_SUBM
 BUFG_PHASE_CLKDV_SUBM


Technical Support:

http://www.xilinx.com/support/support.htm