bufg_dfs_subm.v

本示例中使用了一个DCM模块

//
// Module:      BUFG_DFS_SUBM
//
// Description: Verilog Submodule
//  DCM with CLKFX and CLKFX180 outputs without phase relation to CLK_IN
//  
// Device:  Spartan-3 Family 
//
//---------------------------------------------------------------------

module BUFG_DFS_SUBM ( 
                      CLK_IN,
                      RST,
                      CLKFX,
                      CLKFX180,
                      LOCK
                     );

    input CLK_IN;
    input RST;

    output CLKFX;
    output CLKFX180;
    output LOCK;

    wire CLKFX_W;
    wire CLKFX180_W;
    wire GND;

    assign GND = 1'b0;

    // The synthesis tools should infer an IBUFG for the CLK_IN input. If not, 
    // an IBUFG must be instantiated for CLK_IN.

    // BUFG Instantiation for CLKFX//
    BUFG U0_BUFG (  
                  .I(CLKFX_W),
                  .O(CLKFX)
                 );
    
    // BUFG Instantiation for CLKFX180//
    BUFG U1_BUFG (  
                  .I(CLKFX180_W),
                  .O(CLKFX180)
                 );
 
    // Attributes for functional simulation//
    // synopsys translate_off
       defparam U_DCM.DFS_FREQUENCY_MODE = "LOW";
       defparam U_DCM.CLK_FEEDBACK = "NONE";
       defparam U_DCM.CLKFX_DIVIDE = 1;
       defparam U_DCM.CLKFX_MULTIPLY = 4;
       defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
     DCM U_DCM ( 
                .CLKIN(CLK_IN), 
                .CLKFB(GND), 
                .DSSEN(GND), 
                .PSCLK(GND), 
                .PSEN(GND), 
                .PSINCDEC(GND), 
                .RST(RST), 
                .CLKFX(CLKFX_W), 
                .CLKFX180(CLKFX180_W), 
                .LOCKED(LOCK)
               );
                  
   // synthesis attribute declarations
     /* synopsys attribute 
     DFS_FREQUENCY_MODE "LOW"
     CLK_FEEDBACK "NONE"
     CLKFX_DIVIDE "1"
     CLKFX_MULTIPLY "4"
     STARTUP_WAIT "FALSE"
     */
endmodule