data_count.v

UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例

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//                __     ___ _               ___ ____                         //
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////////////////////////////////////////////////////////////////////////////////
// 	   Copyright (C) 2003-2006 VibesIC, Inc.   All rights reserved.           //
//----------------------------------------------------------------------------//
// This source code is provided by VibesIC,and be verified on VibesIC FPGA    //
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////////////////////////////////////////////////////////////////////////////////
//  Company:       www.richic.com                                             //
//  Company bbs:   www.edacn.net                                              //
//  Engineer:      alex_yang                                                  //
//                                                                            //
//  Target Device: XC3S400-PQ208                                              //
//  Tool versions: Simulation:    ModelSim SE 6.2a                            //
//                 Synthesis:     XST(ise8.1...sp3)                           //
//                 Place&Routing: ISE8.1...sp3                                //
//                 Others tools:  UltraEdit-32 12.10a                         //
//  Create Date:   2006-9-9 18:29                                             //
//  Description:                                                              //
//                                                                            //
//  LOG:                                                                      //
//       1. Revision 1.0 (Initial version)  2006-9-8 18:29    alex_yang       //
//                                                                            //
//       2. Revision 1.1  2006-12-20 16:09   alex_yang                        //
//          Modify for VX-SP306                                               //
////////////////////////////////////////////////////////////////////////////////

module data_count(
    clk,
    rst_n,
    data_out,
    data_out_flag
    );

  input             clk;
  input             rst_n; 
  output reg [7:0]  data_out; 
  output reg        data_out_flag;
 
//  reg led_temp;
  reg [22:0]  clk_cnt;
  always @ (posedge clk)
    if (!rst_n)
      clk_cnt <= 23'd0;
    else
      clk_cnt <= clk_cnt + 1'b1;
      
  always @ (posedge clk)
    if (!rst_n)
      data_out <= 8'd0;
    else if (data_out == 8'd250)
      data_out <= 8'd250;
    else if (clk_cnt == 23'h7f_ffff)
      data_out <= data_out + 1'b1; 
      
  always @ (posedge clk)
    if (!rst_n)
      data_out_flag <= 1'b0;
    else if (data_out == 8'd250)
      data_out_flag <= 1'b0;
    else if (clk_cnt == 23'h7f_ffff)
      data_out_flag <= 1'b1;
    else 
      data_out_flag <= 1'b0;
endmodule