uart_debug.v

UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例

////////////////////////////////////////////////////////////////////////////////
//                __     ___ _               ___ ____                         //
//                \ \   / (_) |__   ___  ___|_ _/ ___|                        //
//                 \ \ / /| | '_ \ / _ \/ __|| | |                            //
//                  \ V / | | |_) |  __/\__ \| | |___                         //
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//                                                                            //
////////////////////////////////////////////////////////////////////////////////
// 	   Copyright (C) 2003-2006 VibesIC, Inc.   All rights reserved.           //
//----------------------------------------------------------------------------//
// This source code is provided by VibesIC,and be verified on VibesIC FPGA    //
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//----------------------------------------------------------------------------//
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////////////////////////////////////////////////////////////////////////////////
//  Company:       www.richic.com                                             //
//  Company bbs:   www.edacn.net                                              //
//  Engineer:      alex_yang                                                  //
//                                                                            //
//  Target Device: XC3S400-PQ208                                              //
//  Tool versions: Simulation:    ModelSim SE 6.2a                            //
//                 Synthesis:     XST(ise8.1...sp3)                           //
//                 Place&Routing: ISE8.1...sp3                                //
//                 Others tools:  UltraEdit-32 12.10a                         //
//  Create Date:   2006-10-16 10:02                                           //
//  Description:                                                              //
//                                                                            //
//  LOG:                                                                      //
//       1. Revision 1.0 (Initial version)  2006-10-16 10:02    alex_yang     //
//                                                                            //
//       2. Revision 1.1  2006-12-20 16:09   alex_yang                        //
//          Modify for VX-SP306                                               //
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ns

module uart_debug(
	  clk,
	  rst_n,
	  rs232_tx_load_request,
	  rs232_tx_load,
	  rs232_tx_data,
	  rs232_rx_data_ready,
	  rs232_rx_data,
	  rs232_rx_read,	  
	  rs232_r1,
	  rs232_t1
//	  rs232_r2,
//    rs232_t2
    );
input	        clk;
input	        rst_n;
output        rs232_tx_load_request;
input	        rs232_tx_load;
input	 [7:0]  rs232_tx_data;

input         rs232_rx_read;
output        rs232_rx_data_ready;
output [7:0]  rs232_rx_data;
input         rs232_r1;
output        rs232_t1;
//input         rs232_r2;
//output        rs232_t2;

wire [2:0] rs232_rx_error;
//-----------------------------------------------------------    
// These defines are for the rs232 interface
`define START_BITS 1
`define DATA_BITS 8
`define STOP_BITS 1
`define CLOCK_FACTOR 16

// This unit generates the correct 16x transmit clock (enable) frequency
// which is used for the serial transmit operation.
clock_gen_select clock_unit
  (
   .clk(clk),
   .reset(!rst_n),
   .rate_select(3'b100),         // 115,200 baud
   .clk_out(serial_clk_16x)
  );


// A transmitter, which asserts load_request at the end of the currently
// transmitted word.  The tx_clk must be a "clock enable" (narrow positive
// pulse) which occurs at 16x the desired transmit rate.  If load_request
// is connected directly to load, the unit will transmit continuously.
rs232tx #(
          `START_BITS,   // start_bits
          `DATA_BITS,    // data_bits
          `STOP_BITS,    // stop_bits (add intercharacter delay...)
          `CLOCK_FACTOR  // clock_factor
         )
         rs232_tx_block  // instance name
         ( 
          .clk(clk),
          .tx_clk(serial_clk_16x),
          .reset(!rst_n),
          .load(rs232_tx_load),
          .data(rs232_tx_data),
          .load_request(rs232_tx_load_request),
          .txd(rs232_t1)
         );

// A receiver, which asserts "word_ready" to indicate a received word.
// Asserting "read_word" will cause "word_ready" to go low again if it was high.
// The character is held in the output register, during the time the next
//   character is coming in.
rs232rx #(
          `START_BITS,  // start_bits
          `DATA_BITS,   // data_bits
          `STOP_BITS,   // stop_bits
          `CLOCK_FACTOR // clock_factor
         )
         rs232_rx_block // instance name
         ( 
          .clk(clk),
          .rx_clk(serial_clk_16x),
          .reset((!rst_n) || (|rs232_rx_error)),
          .rxd(rs232_r1),
          .read(rs232_rx_read),
          .data(rs232_rx_data),
          .data_ready(rs232_rx_data_ready),
          .error_over_run(rs232_rx_error[0]),
          .error_under_run(rs232_rx_error[1]),
          .error_all_low(rs232_rx_error[2])
         );

//`undef START_BITS 
//`undef DATA_BITS 
//`undef STOP_BITS 
//`undef CLOCK_FACTOR

endmodule