debug_top.v

UART接口被广泛应用在程序调适和信息输出。本实验将介绍UART接口的自测和调试实 例

////////////////////////////////////////////////////////////////////////////////
//                __     ___ _               ___ ____                         //
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//                                                                            //
////////////////////////////////////////////////////////////////////////////////
// 	   Copyright (C) 2003-2006 VibesIC, Inc.   All rights reserved.           //
//----------------------------------------------------------------------------//
// This source code is provided by VibesIC,and be verified on VibesIC FPGA    //
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////////////////////////////////////////////////////////////////////////////////
//  Company:       www.richic.com                                             //
//  Company bbs:   www.edacn.net                                              //
//  Engineer:      alex_yang                                                  //
//                                                                            //
//  Target Device: XC3S400-PQ208                                              //
//  Tool versions: Simulation:    ModelSim SE 6.2a                            //
//                 Synthesis:     XST(ise8.1...sp3)                           //
//                 Place&Routing: ISE8.1...sp3                                //
//                 Others tools:  UltraEdit-32 12.10a                         //
//  Create Date:   2006-10-16 10:02                                           //
//  Description:                                                              //
//                                                                            //
//  LOG:                                                                      //
//       1. Revision 1.0 (Initial version)  2006-10-16 10:02    alex_yang     //
//                                                                            //
//       2. Revision 1.1  2006-12-20 16:09   alex_yang                        //
//          Modify for VX-SP306                                               //
////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ns

module debug_top(
	  clk,
	  rst_n,
	  rs232_r1,
	  rs232_t1
    );
input	     clk;
input	     rst_n;
input      rs232_r1;
output     rs232_t1;


wire rs232_rx_data_ready;
wire rs232_rx_read;
wire rs232_tx_load_request;
wire [7:0] rs232_rx_data;
wire [7:0] rs232_tx_data;
wire new_data_flag;


   data_count   data_count_inst (
      .clk            ( clk ),
      .rst_n          ( rst_n ),
      .data_out       ( rs232_tx_data ), 
      .data_out_flag  ( new_data_flag )
   );

// ---------------------------------------------------------------------------
// 例化uart_debug的驱动程序
// ---------------------------------------------------------------------------
  uart_debug uart_debug_inst(
      .clk                    ( clk ),
      .rst_n                  ( rst_n ),
      .rs232_tx_load_request  ( rs232_tx_load_request ),
	    .rs232_tx_load          ( rs232_tx_load_request && new_data_flag ),
	    .rs232_tx_data          ( rs232_tx_data ),
	    .rs232_rx_data_ready    ( rs232_rx_data_ready ),
	    .rs232_rx_data          ( rs232_rx_data ),
	    .rs232_rx_read          ( rs232_rx_read ),
	    .rs232_r1               ( rs232_r1 ),
	    .rs232_t1               ( rs232_t1 )
      );
 
endmodule