📄 rs232_top.v
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////////////////////////////////////////////////////////////////////////////////// __ ___ _ ___ ____ //// \ \ / (_) |__ ___ ___|_ _/ ___| //// \ \ / /| | '_ \ / _ \/ __|| | | //// \ V / | | |_) | __/\__ \| | |___ //// \_/ |_|_.__/ \___||___/___\____| //// //////////////////////////////////////////////////////////////////////////////////// Copyright (C) 2003-2006 VibesIC, Inc. All rights reserved. ////----------------------------------------------------------------------------//// This source code is provided by VibesIC,and be verified on VibesIC FPGA //// development kit. The source code may be used and distributed without //// restriction provided that this copyright statement is not removed from the //// file and that any derivative work contains the original copyright notice //// and the associated disclaimer. ////----------------------------------------------------------------------------//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED //// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF //// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE//// AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, //// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,//// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,OR PROFITS; //// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR //// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF //// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////----------------------------------------------------------------------------//// 本设计由威百仕( VibesIC )提供，并在其产品中验证通过，您可以在此基础上修改，//// 复制并分发,但请您保留版权声明部分。我们并不承诺本设计可以用做商业产品，同时//// 我们不保证设计的通用性。为了方便更新以及修改请保留设计的版本信息，并对自行 //// 修改部分添加足够的注释。对设计如有其他建议,请到网站进行讨论。 //// //////////////////////////////////////////////////////////////////////////////////// Company: www.richic.com //// Company bbs: www.edacn.net //// Engineer: alex_yang //// //// Target Device: XC3S400-PQ208 //// Tool versions: Simulation: ModelSim SE 6.2a //// Synthesis: XST(ise8.1...sp3) //// Place&Routing: ISE8.1...sp3 //// Others tools: UltraEdit-32 12.10a //// Create Date: 2006-10-16 10:02 //// Description: //// //// LOG: //// 1. Revision 1.0 (Initial version) 2006-10-16 10:02 alex_yang //// //// 2. Revision 1.1 2006-12-20 16:09 alex_yang //// Modify for VX-SP306 //////////////////////////////////////////////////////////////////////////////////`timescale 1ns/1nsmodule rs232_top( clk, rst_n, rs232_r1, rs232_t1,// rs232_r2,// rs232_t2 );input clk;input rst_n;input rs232_r1;output rs232_t1;//input rs232_r2;//output rs232_t2;wire [2:0] rs232_rx_error;wire rs232_rx_data_ready;wire rs232_rx_read;wire rs232_tx_load_request;wire rs232_tx_load;wire [7:0] rs232_rx_data;wire [7:0] rs232_tx_data;wire [7:0] rs232_data;//用于将接收到的数据又回传给PC。(形成一个test loop)//需要注意的是：在发送数据时，两个数据之间必须有间隔！否则后面紧接的数据会丢失。//若要避免这种情况，可以考虑添加数据缓存FIFO。assign rs232_data = rs232_rx_data_ready ? rs232_rx_data : 8'b00000000;assign rs232_rx_read = rs232_rx_data_ready ? 1'b1 : 1'b0;assign rs232_tx_data = rs232_rx_data_ready ? rs232_data : 8'b00000000;assign rs232_tx_load = rs232_rx_data_ready ? 1'b1 : 1'b0;//----------------------------------------------------------- // These defines are for the rs232 interface`define START_BITS 1`define DATA_BITS 8`define STOP_BITS 1`define CLOCK_FACTOR 16// This unit generates the correct 16x transmit clock (enable) frequency// which is used for the serial transmit operation.clock_gen_select clock_unit ( .clk(clk), .reset(!rst_n), .rate_select(3'b100), // 115,200 baud .clk_out(serial_clk_16x) );// A transmitter, which asserts load_request at the end of the currently// transmitted word. The tx_clk must be a "clock enable" (narrow positive// pulse) which occurs at 16x the desired transmit rate. If load_request// is connected directly to load, the unit will transmit continuously.rs232tx #( `START_BITS, // start_bits `DATA_BITS, // data_bits `STOP_BITS, // stop_bits (add intercharacter delay...) `CLOCK_FACTOR // clock_factor ) rs232_tx_block // instance name ( .clk(clk), .tx_clk(serial_clk_16x), .reset(!rst_n), .load(rs232_tx_load), .data(rs232_tx_data), .load_request(rs232_tx_load_request), .txd(rs232_t1) );// A receiver, which asserts "word_ready" to indicate a received word.// Asserting "read_word" will cause "word_ready" to go low again if it was high.// The character is held in the output register, during the time the next// character is coming in.rs232rx #( `START_BITS, // start_bits `DATA_BITS, // data_bits `STOP_BITS, // stop_bits `CLOCK_FACTOR // clock_factor ) rs232_rx_block // instance name ( .clk(clk), .rx_clk(serial_clk_16x), .reset((!rst_n) || (|rs232_rx_error)), .rxd(rs232_r1), .read(rs232_rx_read), .data(rs232_rx_data), .data_ready(rs232_rx_data_ready), .error_over_run(rs232_rx_error[0]), .error_under_run(rs232_rx_error[1]), .error_all_low(rs232_rx_error[2]) );//`undef START_BITS //`undef DATA_BITS //`undef STOP_BITS //`undef CLOCK_FACTORendmodule⌨️ 快捷键说明
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