vlsi_ir.h

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 *	  receive fifo until ENRX reenabled _and_ another packet arrives
 *	- SIRFILT means the chip performs the required unwrapping of hardware
 *	  headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction.
 *	  Only the resulting IrLAP payload is copied to the receive buffers -
 *	  but with the 16bit FCS still encluded. Question remains, whether it
 *	  was already checked or we should do it before passing the packet to IrLAP?
 */

enum vlsi_pio_ircfg {
	IRCFG_LOOP	= 0x4000,	/* enable loopback test mode */
	IRCFG_ENTX	= 0x1000,	/* transmit enable */
	IRCFG_ENRX	= 0x0800,	/* receive enable */
	IRCFG_MSTR	= 0x0400,	/* master enable */
	IRCFG_RXANY	= 0x0200,	/* receive any packet */
	IRCFG_CRC16	= 0x0080,	/* 16bit (not 32bit) CRC select for MIR/FIR */
	IRCFG_FIR	= 0x0040,	/* FIR 4PPM encoding mode enable */
	IRCFG_MIR	= 0x0020,	/* MIR HDLC encoding mode enable */
	IRCFG_SIR	= 0x0010,	/* SIR encoding mode enable */
	IRCFG_SIRFILT	= 0x0008,	/* enable SIR decode filter (receiver unwrapping) */
	IRCFG_SIRTEST	= 0x0004,	/* allow SIR decode filter when not in SIR mode */
	IRCFG_TXPOL	= 0x0002,	/* invert tx polarity when set */
	IRCFG_RXPOL	= 0x0001	/* invert rx polarity when set */
};

/* ------------------------------------------ */

/* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */

/* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8]
 * which is used for unwrapping received frames in SIR decode-filter mode
 */

/* ------------------------------------------ */

/* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */

/* notes:
 *	- IREN acts as gate for latching the configured IR mode information
 *	  from IRCFG and IRPHYCTL when IREN=reset and applying them when
 *	  IREN gets set afterwards.
 *	- ENTXST reflects IRCFG_ENTX
 *	- ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP)
 */

enum vlsi_pio_irenable {
	IRENABLE_IREN		= 0x8000,  /* enable IR phy and gate the mode config (rw) */
	IRENABLE_CFGER		= 0x4000,  /* mode configuration error (ro) */
	IRENABLE_FIR_ON		= 0x2000,  /* FIR on status (ro) */
	IRENABLE_MIR_ON		= 0x1000,  /* MIR on status (ro) */
	IRENABLE_SIR_ON		= 0x0800,  /* SIR on status (ro) */
	IRENABLE_ENTXST		= 0x0400,  /* transmit enable status (ro) */
	IRENABLE_ENRXST		= 0x0200,  /* Receive enable status (ro) */
	IRENABLE_CRC16_ON	= 0x0100   /* 16bit (not 32bit) CRC enabled status (ro) */
};

#define	  IRENABLE_MASK	    0xff00  /* Read mask */


/* ------------------------------------------ */

/* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */


/* read-back of the currently applied physical layer status.
 * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_IREN
 * contents identical to VLSI_PIO_NPHYCTL (see below)
 */



/* ------------------------------------------ */


/* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */

/* latched during IRENABLE_IREN=0 and applied at 0-1 transition
 *
 * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows:
 *
 * SIR-mode:	BAUD = (115.2kHz / baudrate) - 1
 *		PLSWID = (pulsetime * freq / (BAUD+1)) - 1
 *			where pulsetime is the requested IrPHY pulse width
 *			and freq is 8(16)MHz for 40(48)MHz primary input clock
 *		PREAMB: dont care for SIR
 *
 *		The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12
 *		fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz).
 *		IrPHY also allows shorter pulses down to the nominal pulse duration
 *		at 115.2kbaud (minus some tolerance) which is 1.41 usec.
 *		Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by to for 48MHz)
 *		we get the minimum acceptable PLSWID values according to the VLSI
 *		specification, which provides 1.5 usec pulse width for all speeds (except
 *		for 2.4kbaud getting 6usec). This is well inside IrPHY v1.3 specs and
 *		reduces the transceiver power which drains the battery. At 9.6kbaud for
 *		example this amounts to more than 90% battery power saving!
 *
 * MIR-mode:	BAUD = 0
 *		PLSWID = 9(10) for 40(48) MHz input clock
 *			to get nominal MIR pulse width
 *		PREAMB = 1
 *
 * FIR-mode:	BAUD = 0
 *		PLSWID: dont care
 *		PREAMB = 15
 */

#define BWP_TO_PHYCTL(B,W,P)	((((B)&0x3f)<<10) | (((W)&0x1f)<<5) | (((P)&0x1f)<<0))
#define BAUD_BITS(br)		((115200/(br))-1)

static inline unsigned
calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect)
{
	unsigned	tmp;

	if (widthselect)	/* nominal 3/16 puls width */
		return (clockselect) ? 12 : 24;

	tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1);

	/* intermediate result of integer division needed here */

	return (tmp>0) ? (tmp-1) : 0;
}


#define PHYCTL_SIR(br,ws,cs)	BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0)
#define PHYCTL_MIR(cs)		BWP_TO_PHYCTL(0,((cs)?9:10),1)
#define PHYCTL_FIR		BWP_TO_PHYCTL(0,0,15)

/* quite ugly, I know. But implementing these calculations here avoids
 * having magic numbers in the code and allows some playing with pulsewidths
 * without risk to violate the standards.
 * FWIW, here is the table for reference:
 *
 * baudrate	BAUD	min-PLSWID	nom-PLSWID	PREAMB
 *     2400	  47	   0(0)		   12(24)	   0
 *     9600	  11	   0(0)		   12(24)	   0
 *    19200	   5	   1(2)		   12(24)	   0
 *    38400	   2	   3(6)	           12(24)	   0
 *    57600	   1	   5(10)	   12(24)	   0
 *   115200	   0	  11(22)	   12(24)	   0
 *	MIR	   0	    -		    9(10)	   1
 *	FIR	   0        -               0		  15
 *
 * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock
 */

/* ------------------------------------------ */


/* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */

/* specifies the maximum legth (up to 4k - or (4k-1)? - bytes), which a
 * received frame may have - i.e. the size of the corresponding
 * receive buffers. For simplicity we use the same length for
 * receive and submit buffers and increase transfer buffer size
 * byond IrDA-MTU = 2048 so we have sufficient space left when
 * packet size increases during wrapping due to XBOFs and CE's.
 * Even for receiving unwrapped frames we need >MAX_PACKET_LEN
 * space since the controller appends FCS/CRC (2 or 4 bytes)
 * so we use 2*IrDA-MTU for both directions and cover even the
 * worst case, where all data bytes have to be escaped when wrapping.
 * well, this wastes some memory - anyway, later we will
 * either map skb's directly or use pci_pool allocator...
 */
 
#define IRDA_MTU	2048		/* seems to be undefined elsewhere */
 
#define XFER_BUF_SIZE		(2*IRDA_MTU)

#define MAX_PACKET_LENGTH	(XFER_BUF_SIZE-1) /* register uses only [11:0] */


/* ------------------------------------------ */


/* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */

/* recive packet counter gets incremented on every non-filtered
 * byte which was put in the receive fifo and reset for each
 * new packet. Used to decide whether we are just in the middle
 * of receiving
 */

#define RCVBCNT_MASK	0x0fff

/* ================================================================ */


/* descriptors for rx/tx ring
 *
 * accessed by hardware - don't change!
 *
 * the descriptor is owned by hardware, when the ACTIVE status bit
 * is set and nothing (besides reading status to test the bit)
 * shall be done. The bit gets cleared by hw, when the descriptor
 * gets closed. Premature reaping of descriptors owned be the chip
 * can be achieved by disabling IRCFG_MSTR
 *
 * Attention: Writing addr overwrites status!
 *
 * ### FIXME: we depend on endianess here
 */

struct ring_descr {
	volatile u16	rd_count;	/* tx/rx count [11:0] */
	u16		reserved;
	union {
		u32	addr;		/* [23:0] of the buffer's busaddress */
		struct {
			u8		addr_res[3];
			volatile u8	status;		/* descriptor status */
		} rd_s;
	} rd_u;
};

#define rd_addr		rd_u.addr
#define rd_status	rd_u.rd_s.status


/* ring descriptor status bits */

#define RD_STAT_ACTIVE		0x80	/* descriptor owned by hw (both TX,RX) */

/* TX ring descriptor status */

#define	TX_STAT_DISCRC		0x40	/* do not send CRC (for SIR) */
#define	TX_STAT_BADCRC		0x20	/* force a bad CRC */
#define	TX_STAT_PULSE		0x10	/* send indication pulse after this frame (MIR/FIR) */
#define	TX_STAT_FRCEUND		0x08	/* force underrun */
#define	TX_STAT_CLRENTX		0x04	/* clear ENTX after this frame */
#define	TX_STAT_UNDRN		0x01	/* TX fifo underrun (probably PCI problem) */

/* RX ring descriptor status */

#define RX_STAT_PHYERR		0x40	/* physical encoding error */
#define RX_STAT_CRCERR		0x20	/* CRC error (MIR/FIR) */
#define RX_STAT_LENGTH		0x10	/* frame exceeds buffer length */
#define RX_STAT_OVER		0x08	/* RX fifo overrun (probably PCI problem) */
#define RX_STAT_SIRBAD		0x04	/* EOF missing: BOF follows BOF (SIR, filtered) */


#define RX_STAT_ERROR		0x7c	/* any error in frame */


/* ------------------------------------------ */

/* contains the objects we've put into the ring descriptors
 * static buffers for now - probably skb's later
 */

struct ring_entry {
	struct sk_buff	*skb;
	void		*data;
};


struct vlsi_ring {
	unsigned		size;
	unsigned		mask;
	unsigned		head, tail;
	struct ring_descr	*hw;
	struct ring_entry	buf[MAX_RING_DESCR];
};

/* ------------------------------------------ */

/* our private compound VLSI-PCI-IRDA device information */

typedef struct vlsi_irda_dev {
	struct pci_dev		*pdev;
	struct net_device_stats	stats;

	struct irlap_cb		*irlap;

	struct qos_info		qos;

	unsigned		mode;
	int			baud, new_baud;

	dma_addr_t		busaddr;
	void			*virtaddr;
	struct vlsi_ring	tx_ring, rx_ring;

	struct timeval		last_rx;

	spinlock_t		lock;
	
} vlsi_irda_dev_t;

/********************************************************/

#endif /* IRDA_VLSI_FIR_H */