pgtable.h

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/* CRIS pgtable.h - macros and functions to manipulate page tables
 *
 * HISTORY:
 *
 * $Log: pgtable.h,v $
 * Revision 1.14  2001/12/10 03:08:50  bjornw
 * Added pgtable_cache_init dummy
 *
 * Revision 1.13  2001/11/12 18:05:38  pkj
 * Added declaration of paging_init().
 *
 * Revision 1.12  2001/08/11 00:28:00  bjornw
 * PAGE_CHG_MASK and PAGE_NONE had somewhat untraditional values
 *
 * Revision 1.11  2001/04/04 14:38:36  bjornw
 * Removed bad_pagetable handling and the _kernel functions
 *
 * Revision 1.10  2001/03/23 07:46:42  starvik
 * Corrected according to review remarks
 *
 * Revision 1.9  2000/11/22 14:57:53  bjornw
 * * extern inline -> static inline
 * * include asm-generic/pgtable.h
 *
 * Revision 1.8  2000/11/21 13:56:16  bjornw
 * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type
 *
 * Revision 1.7  2000/10/06 15:05:32  bjornw
 * VMALLOC area changed in memory mapping change
 *
 * Revision 1.6  2000/10/04 16:59:14  bjornw
 * Changed comments
 *
 * Revision 1.5  2000/09/13 14:39:53  bjornw
 * New macros
 *
 * Revision 1.4  2000/08/17 15:38:48  bjornw
 * 2.4.0-test6 modifications:
 *   * flush_dcache_page added
 *   * MAP_NR removed
 *   * virt_to_page added
 *
 * Plus some comments and type-clarifications.
 *
 * Revision 1.3  2000/08/15 16:33:35  bjornw
 * pmd_bad should recognize both kernel and user page-tables
 *
 * Revision 1.2  2000/07/10 17:06:01  bjornw
 * Fixed warnings
 *
 * Revision 1.1.1.1  2000/07/10 16:32:31  bjornw
 * CRIS architecture, working draft
 *
 *
 * Revision 1.11  2000/05/29 14:55:56  bjornw
 * Small tweaks of pte_mk routines
 *
 * Revision 1.10  2000/01/27 01:49:06  bjornw
 * * Ooops. The physical frame number in a PTE entry needs to point to the
 *   DRAM directly, not to what the kernel thinks is DRAM (due to KSEG mapping).
 *   Hence we need to strip bit 31 so 0xcXXXXXXX -> 0x4XXXXXXX.
 *
 * Revision 1.9  2000/01/26 16:25:50  bjornw
 * Fixed PAGE_KERNEL bits
 *
 * Revision 1.8  2000/01/23 22:53:22  bjornw
 * Correct flush_tlb_* macros and externs
 *
 * Revision 1.7  2000/01/18 16:22:55  bjornw
 * Use PAGE_MASK instead of PFN_MASK.
 *
 * Revision 1.6  2000/01/17 02:42:53  bjornw
 * Added the pmd_set macro.
 *
 * Revision 1.5  2000/01/16 19:53:42  bjornw
 * Removed VMALLOC_OFFSET. Changed definitions of swapper_pg_dir and zero_page.
 *
 * Revision 1.4  2000/01/14 16:38:20  bjornw
 * PAGE_DIRTY -> PAGE_SILENT_WRITE, removed PAGE_COW from PAGE_COPY.
 *
 * Revision 1.3  1999/12/04 20:12:21  bjornw
 * * PTE bits have moved to asm/mmu.h
 * * Fixed definitions of the higher level page protection bits
 * * Added the pte_* functions, including dirty/accessed SW simulation
 *   (these are exactly the same as for the MIPS port)
 *
 * Revision 1.2  1999/12/04 00:41:54  bjornw
 * * Fixed page table offsets, sizes and shifts
 * * Removed reference to i386 SMP stuff
 * * Added stray comments about Linux/CRIS mm design
 * * Include asm/mmu.h which will contain MMU details
 *
 * Revision 1.1  1999/12/03 15:04:02  bjornw
 * Copied from include/asm-etrax100. For the new CRIS architecture.
 */

#ifndef _CRIS_PGTABLE_H
#define _CRIS_PGTABLE_H

#include <linux/config.h>
#include <asm/mmu.h>

/*
 * The Linux memory management assumes a three-level page table setup. On
 * CRIS, we use that, but "fold" the mid level into the top-level page
 * table. Since the MMU TLB is software loaded through an interrupt, it
 * supports any page table structure, so we could have used a three-level
 * setup, but for the amounts of memory we normally use, a two-level is
 * probably more efficient.
 *
 * This file contains the functions and defines necessary to modify and use
 * the CRIS page table tree.
 */

extern void paging_init(void);

/* The cache doesn't need to be flushed when TLB entries change because 
 * the cache is mapped to physical memory, not virtual memory
 */
#define flush_cache_all()			do { } while (0)
#define flush_cache_mm(mm)			do { } while (0)
#define flush_cache_range(mm, start, end)	do { } while (0)
#define flush_cache_page(vma, vmaddr)		do { } while (0)
#define flush_page_to_ram(page)			do { } while (0)
#define flush_dcache_page(page)                 do { } while (0)
#define flush_icache_range(start, end)          do { } while (0)
#define flush_icache_page(vma,pg)               do { } while (0)

/*
 * TLB flushing (implemented in arch/cris/mm/tlb.c):
 *
 *  - flush_tlb() flushes the current mm struct TLBs
 *  - flush_tlb_all() flushes all processes TLBs
 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 *  - flush_tlb_page(vma, vmaddr) flushes one page
 *  - flush_tlb_range(mm, start, end) flushes a range of pages
 *
 */

extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_page(struct vm_area_struct *vma, 
			   unsigned long addr);
extern void flush_tlb_range(struct mm_struct *mm,
			    unsigned long start,
			    unsigned long end);

static inline void flush_tlb_pgtables(struct mm_struct *mm,
                                      unsigned long start, unsigned long end)
{
        /* CRIS does not keep any page table caches in TLB */
}


static inline void flush_tlb(void) 
{
	flush_tlb_mm(current->mm);
}

/* Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
/*
 * (pmds are folded into pgds so this doesnt get actually called,
 * but the define is needed for a generic inline function.)
 */
#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)

/* PMD_SHIFT determines the size of the area a second-level page table can
 * map. It is equal to the page size times the number of PTE's that fit in
 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
 */

#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map.
 * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
 */

#define PGDIR_SHIFT	PMD_SHIFT
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * entries per page directory level: we use a two-level, so
 * we don't really have any PMD directory physically.
 * pointers are 4 bytes so we can use the page size and 
 * divide it by 4 (shift by 2).
 */
#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
#define PTRS_PER_PMD	1
#define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-2))

/* calculate how many PGD entries a user-level program can use
 * the first mappable virtual address is 0
 * (TASK_SIZE is the maximum virtual address space)
 */

#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_PGD_NR       0

/*
 * Kernels own virtual memory area. 
 */

#ifdef CONFIG_CRIS_LOW_MAP
#define VMALLOC_START     KSEG_7
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END       KSEG_8
#else
#define VMALLOC_START     KSEG_D
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END       KSEG_E
#endif

/* Define some higher level generic page attributes. The PTE bits are
 * defined in asm-cris/mmu.h, and these are just combinations of those.
 */

#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)

#define _PAGE_TABLE     (_PAGE_PRESENT | __READABLE | __WRITEABLE)
#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)

#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
				 _PAGE_ACCESSED)
#define PAGE_COPY       __pgprot(_PAGE_PRESENT | __READABLE)  // | _PAGE_COW
#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | __READABLE)
#define PAGE_KERNEL     __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
				 _PAGE_PRESENT | __READABLE | __WRITEABLE)
#define _KERNPG_TABLE   (_PAGE_TABLE | _PAGE_KERNEL)

/*
 * CRIS can't do page protection for execute, and considers read the same.
 * Also, write permissions imply read permissions. This is the closest we can
 * get..
 */

#define __P000	PAGE_NONE
#define __P001	PAGE_READONLY
#define __P010	PAGE_COPY
#define __P011	PAGE_COPY
#define __P100	PAGE_READONLY
#define __P101	PAGE_READONLY
#define __P110	PAGE_COPY
#define __P111	PAGE_COPY

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY
#define __S101	PAGE_READONLY
#define __S110	PAGE_SHARED