sal.h

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            bank            : 1,
            device          : 1,
            row             : 1,
            column          : 1,
            bit_position    : 1,
            requestor_id    : 1,
            responder_id    : 1,
            target_id       : 1,
            bus_spec_data   : 1,
            oem_id          : 1,
            oem_data        : 1,
            reserved        : 47;
    } valid;
    u64             error_status;
    u64             physical_addr;
    u64             addr_mask;
    u16             node;
    u16             card;
    u16             module;
    u16             bank;
    u16             device;
    u16             row;
    u16             column;
    u16             bit_position;
    u64             requestor_id;
    u64             responder_id;
    u64             target_id;
    u64             bus_spec_data;
    u8              oem_id[16];
    u8              oem_data[1];        /* Variable length data */
} sal_log_mem_dev_err_info_t;

typedef struct sal_log_sel_dev_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 record_id       : 1,
            record_type     : 1,
            generator_id    : 1,
            evm_rev         : 1,
            sensor_type     : 1,
            sensor_num      : 1,
            event_dir       : 1,
            event_data1     : 1,
            event_data2     : 1,
            event_data3     : 1,
            reserved        : 54;
    } valid;
    u16             record_id;
    u8              record_type;
    u8              timestamp[4];
    u16             generator_id;
    u8              evm_rev;
    u8              sensor_type;
    u8              sensor_num;
    u8              event_dir;
    u8              event_data1;
    u8              event_data2;
    u8              event_data3;
} sal_log_sel_dev_err_info_t;

typedef struct sal_log_pci_bus_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 err_status      : 1,
            err_type        : 1,
            bus_id          : 1,
            bus_address     : 1,
            bus_data        : 1,
            bus_cmd         : 1,
            requestor_id    : 1,
            responder_id    : 1,
            target_id       : 1,
            oem_data        : 1,
            reserved        : 54;
    } valid;
    u64             err_status;
    u16             err_type;
    u16             bus_id;
    u32             reserved;
    u64             bus_address;
    u64             bus_data;
    u64             bus_cmd;
    u64             requestor_id;
    u64             responder_id;
    u64             target_id;
    u8              oem_data[1];        /* Variable length data */
} sal_log_pci_bus_err_info_t;

typedef struct sal_log_smbios_dev_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 event_type      : 1,
            length          : 1,
            time_stamp      : 1,
            data            : 1,
            reserved1       : 60;
    } valid;
    u8              event_type;
    u8              length;
    u8              time_stamp[6];
    u8              data[1];  // data of variable length, length == slsmb_length
} sal_log_smbios_dev_err_info_t;

typedef struct sal_log_pci_comp_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 err_status      : 1,
            comp_info       : 1,
            num_mem_regs    : 1,
            num_io_regs     : 1,
            reg_data_pairs  : 1,
            oem_data        : 1,
            reserved        : 58;
    } valid;
    u64             err_status;
    struct
    {
        u16 vendor_id;
        u16 device_id;
        u16 class_code;
        u8  func_num;
        u8  dev_num;
        u8  bus_num;
        u8  seg_num;
        u8  reserved[6];
    }               comp_info;
    u32             num_mem_regs;
    u32             num_io_regs;
    u64             reg_data_pairs[1];
    /* array of address/data register pairs is num_mem_regs + num_io_regs
       elements long.  Each array element consists of a u64 address followed
       by a u64 data value.  The oem_data array immediately follows the the
       reg_data_pairs array */
    u8              oem_data[1];        /* Variable length data */
} sal_log_pci_comp_err_info_t;

typedef struct sal_log_plat_specific_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 err_status      : 1,
            guid            : 1,
            oem_data        : 1,
            reserved        : 61;
    } valid;
    u64             err_status;
    efi_guid_t      guid;
    u8              oem_data[1];      /* platform specific variable length data */
} sal_log_plat_specific_err_info_t;

typedef struct sal_log_host_ctlr_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 err_status      : 1,
            requestor_id    : 1,
            responder_id    : 1,
            target_id       : 1,
            bus_spec_data   : 1,
            oem_data        : 1,
            reserved        : 58;
    } valid;
    u64             err_status;
    u64             requestor_id;
    u64             responder_id;
    u64             target_id;
    u64             bus_spec_data;
    u8              oem_data[1];        /* Variable length OEM data */
} sal_log_host_ctlr_err_info_t;

typedef struct sal_log_plat_bus_err_info
{
    sal_log_section_hdr_t   header;
    struct
    {
        u64 err_status      : 1,
            requestor_id    : 1,
            responder_id    : 1,
            target_id       : 1,
            bus_spec_data   : 1,
            oem_data        : 1,
            reserved        : 58;
    } valid;
    u64             err_status;
    u64             requestor_id;
    u64             responder_id;
    u64             target_id;
    u64             bus_spec_data;
    u8              oem_data[1];        /* Variable length OEM data */
} sal_log_plat_bus_err_info_t;

/* Overall platform error section structure */
typedef union sal_log_platform_err_info
{
    sal_log_mem_dev_err_info_t          mem_dev_err;
    sal_log_sel_dev_err_info_t          sel_dev_err;
    sal_log_pci_bus_err_info_t          pci_bus_err;
    sal_log_smbios_dev_err_info_t       smbios_dev_err;
    sal_log_pci_comp_err_info_t         pci_comp_err;
    sal_log_plat_specific_err_info_t    plat_specific_err;
    sal_log_host_ctlr_err_info_t        host_ctlr_err;
    sal_log_plat_bus_err_info_t         plat_bus_err;
} sal_log_platform_err_info_t;

/* SAL log over-all, multi-section error record structure (processor+platform) */
typedef struct err_rec
{
    sal_log_record_header_t     sal_elog_header;
    sal_log_processor_info_t    proc_err;
    sal_log_platform_err_info_t plat_err;
    u8                          oem_data_pad[1024];
} ia64_err_rec_t;

/*
 * Now define a couple of inline functions for improved type checking
 * and convenience.
 */
static inline long
ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
		    unsigned long *drift_info)
{
	struct ia64_sal_retval isrv;

	SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
	*ticks_per_second = isrv.v0;
	*drift_info = isrv.v1;
	return isrv.status;
}

/* Flush all the processor and platform level instruction and/or data caches */
static inline s64
ia64_sal_cache_flush (u64 cache_type)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}


	
/* Initialize all the processor and platform level instruction and data caches */
static inline s64
ia64_sal_cache_init (void)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}

/* Clear the processor and platform information logged by SAL with respect to the 
 * machine state at the time of MCA's, INITs, CMCs, or CPEs.
 */
static inline s64
ia64_sal_clear_state_info (u64 sal_info_type)
{
	struct ia64_sal_retval isrv;
    SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
             0, 0, 0, 0, 0);
	return isrv.status;
}


/* Get the processor and platform information logged by SAL with respect to the machine
 * state at the time of the MCAs, INITs, CMCs, or CPEs.
 */
static inline u64
ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
	         sal_info, 0, 0, 0, 0);
	if (isrv.status)
		return 0;

	return isrv.v0;
}	
/* Get the maximum size of the information logged by SAL with respect to the machine 
 * state at the time of MCAs, INITs, CMCs, or CPEs.
 */
static inline u64
ia64_sal_get_state_info_size (u64 sal_info_type)
{
	struct ia64_sal_retval isrv;
    SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
             0, 0, 0, 0, 0);
	if (isrv.status)
		return 0;
	return isrv.v0;
}

/* Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup
 * from the monarch processor.
 */
static inline s64
ia64_sal_mc_rendez (void)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
	return isrv.status;
}

/* Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
 * the machine check rendezvous sequence as well as the mechanism to wake up the 
 * non-monarch processor at the end of machine check processing.
 */
static inline s64
ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout, rz_always, 0, 0);
	return isrv.status;
}

/* Read from PCI configuration space */
static inline s64
ia64_sal_pci_config_read (u64 pci_config_addr, u64 size, u64 *value)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, 0, 0, 0, 0, 0);
	if (value)
		*value = isrv.v0;
	return isrv.status;
}

/* Write to PCI configuration space */
static inline s64
ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
	         0, 0, 0, 0);
	return isrv.status;
}

/*
 * Register physical addresses of locations needed by SAL when SAL
 * procedures are invoked in virtual mode.
 */
static inline s64
ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
	         0, 0, 0, 0, 0);
	return isrv.status;
}

/* Register software dependent code locations within SAL. These locations are handlers
 * or entry points where SAL will pass control for the specified event. These event
 * handlers are for the bott rendezvous, MCAs and INIT scenarios.
 */
static inline s64
ia64_sal_set_vectors (u64 vector_type,
		      u64 handler_addr1, u64 gp1, u64 handler_len1,
		      u64 handler_addr2, u64 gp2, u64 handler_len2)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
			handler_addr1, gp1, handler_len1,
			handler_addr2, gp2, handler_len2);			

	return isrv.status;
}		
/* Update the contents of PAL block in the non-volatile storage device */
static inline s64
ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
		     u64 *error_code, u64 *scratch_buf_size_needed)
{
	struct ia64_sal_retval isrv;
	SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
	         0, 0, 0, 0);
	if (error_code)
		*error_code = isrv.v0;
	if (scratch_buf_size_needed)
		*scratch_buf_size_needed = isrv.v1;
	return isrv.status;
}

#endif /* _ASM_IA64_PAL_H */