dsp2833x_mcbsp.h

DSP28335外部时钟中断跑马灯程序

   Uint16     RCEF6:1;       // 6   Receive Channel enable bit
   Uint16     RCEF7:1;       // 7   Receive Channel enable bit
   Uint16     RCEF8:1;       // 8   Receive Channel enable bit
   Uint16     RCEF9:1;       // 9   Receive Channel enable bit
   Uint16     RCEF10:1;      // 10  Receive Channel enable bit
   Uint16     RCEF11:1;      // 11  Receive Channel enable bit
   Uint16     RCEF12:1;      // 12  Receive Channel enable bit
   Uint16     RCEF13:1;      // 13  Receive Channel enable bit
   Uint16     RCEF14:1;      // 14  Receive Channel enable bit
   Uint16     RCEF15:1;      // 15  Receive Channel enable bit
};

union RCERF_REG {
   Uint16              all;
   struct  RCERF_BITS  bit;
};

// XCERE control register bit definitions:
struct  XCERE_BITS {         // bit description
   Uint16     XCERE0:1;       // 0   Receive Channel enable bit
   Uint16     XCERE1:1;       // 1   Receive Channel enable bit
   Uint16     XCERE2:1;       // 2   Receive Channel enable bit
   Uint16     XCERE3:1;       // 3   Receive Channel enable bit
   Uint16     XCERE4:1;       // 4   Receive Channel enable bit
   Uint16     XCERE5:1;       // 5   Receive Channel enable bit
   Uint16     XCERE6:1;       // 6   Receive Channel enable bit
   Uint16     XCERE7:1;       // 7   Receive Channel enable bit
   Uint16     XCERE8:1;       // 8   Receive Channel enable bit
   Uint16     XCERE9:1;       // 9   Receive Channel enable bit
   Uint16     XCERE10:1;      // 10  Receive Channel enable bit
   Uint16     XCERE11:1;      // 11  Receive Channel enable bit
   Uint16     XCERE12:1;      // 12  Receive Channel enable bit
   Uint16     XCERE13:1;      // 13  Receive Channel enable bit
   Uint16     XCERE14:1;      // 14  Receive Channel enable bit
   Uint16     XCERE15:1;      // 15  Receive Channel enable bit
};

union XCERE_REG {
   Uint16              all;
   struct  XCERE_BITS  bit;
};

// XCERF control register bit definitions:
struct  XCERF_BITS {         // bit description
   Uint16     XCERF0:1;       // 0   Receive Channel enable bit
   Uint16     XCERF1:1;       // 1   Receive Channel enable bit
   Uint16     XCERF2:1;       // 2   Receive Channel enable bit
   Uint16     XCERF3:1;       // 3   Receive Channel enable bit
   Uint16     XCERF4:1;       // 4   Receive Channel enable bit
   Uint16     XCERF5:1;       // 5   Receive Channel enable bit
   Uint16     XCERF6:1;       // 6   Receive Channel enable bit
   Uint16     XCERF7:1;       // 7   Receive Channel enable bit
   Uint16     XCERF8:1;       // 8   Receive Channel enable bit
   Uint16     XCERF9:1;       // 9   Receive Channel enable bit
   Uint16     XCERF10:1;      // 10  Receive Channel enable bit
   Uint16     XCERF11:1;      // 11  Receive Channel enable bit
   Uint16     XCERF12:1;      // 12  Receive Channel enable bit
   Uint16     XCERF13:1;      // 13  Receive Channel enable bit
   Uint16     XCERF14:1;      // 14  Receive Channel enable bit
   Uint16     XCERF15:1;      // 15  Receive Channel enable bit
};

union XCERF_REG {
   Uint16              all;
   struct  XCERF_BITS  bit;
};

// RCERG control register bit definitions:
struct  RCERG_BITS {         // bit description
   Uint16     RCEG0:1;       // 0   Receive Channel enable bit
   Uint16     RCEG1:1;       // 1   Receive Channel enable bit
   Uint16     RCEG2:1;       // 2   Receive Channel enable bit
   Uint16     RCEG3:1;       // 3   Receive Channel enable bit
   Uint16     RCEG4:1;       // 4   Receive Channel enable bit
   Uint16     RCEG5:1;       // 5   Receive Channel enable bit
   Uint16     RCEG6:1;       // 6   Receive Channel enable bit
   Uint16     RCEG7:1;       // 7   Receive Channel enable bit
   Uint16     RCEG8:1;       // 8   Receive Channel enable bit
   Uint16     RCEG9:1;       // 9   Receive Channel enable bit
   Uint16     RCEG10:1;      // 10  Receive Channel enable bit
   Uint16     RCEG11:1;      // 11  Receive Channel enable bit
   Uint16     RCEG12:1;      // 12  Receive Channel enable bit
   Uint16     RCEG13:1;      // 13  Receive Channel enable bit
   Uint16     RCEG14:1;      // 14  Receive Channel enable bit
   Uint16     RCEG15:1;      // 15  Receive Channel enable bit
};

union RCERG_REG {
   Uint16              all;
   struct  RCERG_BITS  bit;
};

// RCERH control register bit definitions:
struct  RCERH_BITS {         // bit description
   Uint16     RCEH0:1;       // 0   Receive Channel enable bit
   Uint16     RCEH1:1;       // 1   Receive Channel enable bit
   Uint16     RCEH2:1;       // 2   Receive Channel enable bit
   Uint16     RCEH3:1;       // 3   Receive Channel enable bit
   Uint16     RCEH4:1;       // 4   Receive Channel enable bit
   Uint16     RCEH5:1;       // 5   Receive Channel enable bit
   Uint16     RCEH6:1;       // 6   Receive Channel enable bit
   Uint16     RCEH7:1;       // 7   Receive Channel enable bit
   Uint16     RCEH8:1;       // 8   Receive Channel enable bit
   Uint16     RCEH9:1;       // 9   Receive Channel enable bit
   Uint16     RCEH10:1;      // 10  Receive Channel enable bit
   Uint16     RCEH11:1;      // 11  Receive Channel enable bit
   Uint16     RCEH12:1;      // 12  Receive Channel enable bit
   Uint16     RCEH13:1;      // 13  Receive Channel enable bit
   Uint16     RCEH14:1;      // 14  Receive Channel enable bit
   Uint16     RCEH15:1;      // 15  Receive Channel enable bit
};

union RCERH_REG {
   Uint16              all;
   struct  RCERH_BITS  bit;
};

// XCERG control register bit definitions:
struct  XCERG_BITS {         // bit description
   Uint16     XCERG0:1;       // 0   Receive Channel enable bit
   Uint16     XCERG1:1;       // 1   Receive Channel enable bit
   Uint16     XCERG2:1;       // 2   Receive Channel enable bit
   Uint16     XCERG3:1;       // 3   Receive Channel enable bit
   Uint16     XCERG4:1;       // 4   Receive Channel enable bit
   Uint16     XCERG5:1;       // 5   Receive Channel enable bit
   Uint16     XCERG6:1;       // 6   Receive Channel enable bit
   Uint16     XCERG7:1;       // 7   Receive Channel enable bit
   Uint16     XCERG8:1;       // 8   Receive Channel enable bit
   Uint16     XCERG9:1;       // 9   Receive Channel enable bit
   Uint16     XCERG10:1;      // 10  Receive Channel enable bit
   Uint16     XCERG11:1;      // 11  Receive Channel enable bit
   Uint16     XCERG12:1;      // 12  Receive Channel enable bit
   Uint16     XCERG13:1;      // 13  Receive Channel enable bit
   Uint16     XCERG14:1;      // 14  Receive Channel enable bit
   Uint16     XCERG15:1;      // 15  Receive Channel enable bit
};

union XCERG_REG {
   Uint16              all;
   struct  XCERG_BITS  bit;
};

// XCERH control register bit definitions:
struct  XCERH_BITS {         // bit description
   Uint16     XCEH0:1;       // 0   Receive Channel enable bit
   Uint16     XCEH1:1;       // 1   Receive Channel enable bit
   Uint16     XCEH2:1;       // 2   Receive Channel enable bit
   Uint16     XCEH3:1;       // 3   Receive Channel enable bit
   Uint16     XCEH4:1;       // 4   Receive Channel enable bit
   Uint16     XCEH5:1;       // 5   Receive Channel enable bit
   Uint16     XCEH6:1;       // 6   Receive Channel enable bit
   Uint16     XCEH7:1;       // 7   Receive Channel enable bit
   Uint16     XCEH8:1;       // 8   Receive Channel enable bit
   Uint16     XCEH9:1;       // 9   Receive Channel enable bit
   Uint16     XCEH10:1;      // 10  Receive Channel enable bit
   Uint16     XCEH11:1;      // 11  Receive Channel enable bit
   Uint16     XCEH12:1;      // 12  Receive Channel enable bit
   Uint16     XCEH13:1;      // 13  Receive Channel enable bit
   Uint16     XCEH14:1;      // 14  Receive Channel enable bit
   Uint16     XCEH15:1;      // 15  Receive Channel enable bit
};

union XCERH_REG {
   Uint16              all;
   struct  XCERH_BITS  bit;
};


// McBSP Interrupt enable register for RINT/XINT
struct  MFFINT_BITS {       // bits description
    Uint16     XINT:1;      // 0    XINT  interrupt enable
    Uint16     XEVTA:1;     // 1    XEVTA interrupt enable
    Uint16     RINT:1;      // 2    RINT  interrupt enable
    Uint16     REVTA:1;     // 3    REVTA interrupt enable
    Uint16     rsvd:12;     // 15:4 reserved
};

union MFFINT_REG {
   Uint16              all;
   struct MFFINT_BITS  bit;
};


//---------------------------------------------------------------------------
// McBSP Register File:
//
struct  MCBSP_REGS {
   union DRR2_REG    DRR2;       // MCBSP Data receive register bits 31-16
   union DRR1_REG    DRR1;       // MCBSP Data receive register bits 15-0
   union DXR2_REG    DXR2;       // MCBSP Data transmit register bits 31-16
   union DXR1_REG    DXR1;       // MCBSP Data transmit register bits 15-0
   union SPCR2_REG   SPCR2;      // MCBSP control register bits 31-16
   union SPCR1_REG   SPCR1;      // MCBSP control register bits 15-0
   union RCR2_REG    RCR2;       // MCBSP receive control register bits 31-16
   union RCR1_REG    RCR1;       // MCBSP receive control register bits 15-0
   union XCR2_REG    XCR2;       // MCBSP transmit control register bits 31-16
   union XCR1_REG    XCR1;       // MCBSP transmit control register bits 15-0
   union SRGR2_REG   SRGR2;      // MCBSP sample rate gen register bits 31-16
   union SRGR1_REG   SRGR1;      // MCBSP sample rate gen register bits 15-0
   union MCR2_REG    MCR2;       // MCBSP multichannel register bits 31-16
   union MCR1_REG    MCR1;       // MCBSP multichannel register bits 15-0
   union RCERA_REG   RCERA;      // MCBSP Receive channel enable partition A
   union RCERB_REG   RCERB;      // MCBSP Receive channel enable partition B
   union XCERA_REG   XCERA;      // MCBSP Transmit channel enable partition A
   union XCERB_REG   XCERB;      // MCBSP Transmit channel enable partition B
   union PCR_REG     PCR;        // MCBSP Pin control register bits 15-0
   union RCERC_REG   RCERC;      // MCBSP Receive channel enable partition C
   union RCERD_REG   RCERD;      // MCBSP Receive channel enable partition D
   union XCERC_REG   XCERC;      // MCBSP Transmit channel enable partition C
   union XCERD_REG   XCERD;      // MCBSP Transmit channel enable partition D
   union RCERE_REG   RCERE;      // MCBSP Receive channel enable partition E
   union RCERF_REG   RCERF;      // MCBSP Receive channel enable partition F
   union XCERE_REG   XCERE;      // MCBSP Transmit channel enable partition E
   union XCERF_REG   XCERF;      // MCBSP Transmit channel enable partition F
   union RCERG_REG   RCERG;      // MCBSP Receive channel enable partition G
   union RCERH_REG   RCERH;      // MCBSP Receive channel enable partition H
   union XCERG_REG   XCERG;      // MCBSP Transmit channel enable partition G
   union XCERH_REG   XCERH;      // MCBSP Transmit channel enable partition H
   Uint16            rsvd1[4];   // reserved
   union MFFINT_REG  MFFINT;     // MCBSP Interrupt enable register for RINT/XINT
   Uint16            rsvd2;      // reserved
};

//---------------------------------------------------------------------------
// McBSP External References & Function Declarations:
//
extern volatile struct MCBSP_REGS McbspaRegs;
extern volatile struct MCBSP_REGS McbspbRegs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  // end of DSP2833x_MCBSP_H definition

//===========================================================================
// No more.
//===========================================================================