sd_datatype.h

linux 2.6下的sd卡驱动

/***************************************************************************
*   File:    sd_datatype.h  -   Data types for SD
* 
*   The content of this file or document is CONFIDENTIAL and PROPRIETARY
*   to Jade Technologies Co., Ltd.  It is subject to the terms of a
*   License Agreement between Licensee and Jade Technologies Co., Ltd.
*   restricting among other things, the use, reproduction, distribution
*   and transfer.  Each of the embodiments, including this information 
*   and any derivative work shall retain this copyright notice.
* 
*   Copyright (c) 2005 Jade Technologies Co., Ltd. 
*   All rights reserved.
****************************************************************************/
#ifndef SD_DATATYPE_H
#define SD_DATATYPE_H

#include <linux/major.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/blkdev.h>
#include <linux/bitops.h>
#include <linux/delay.h>

#include <linux/hdreg.h>
#include <asm/setup.h>
#include <asm/pgtable.h>

typedef int BOOL;
typedef void * LPVOID;
#define FALSE 0
#define TRUE 1

//#pragma pack(1)
/*
 * Description:
 * This specifies the enable and power save options for the PrimeCell
 * The default mode (apMCI_CLOCK_POWERSAVE) will switch the clock off if unused for
 * a period after a command. 
 */
typedef enum apMCI_xClockMode
{
    apMCI_CLOCK_DISABLED =0x00,        /*Clock wholly disabled*/
    apMCI_CLOCK_ENABLED  =0x01,        /*Clock enabled*/
    apMCI_CLOCK_POWERSAVE=0x03        /*Clock running in power save mode - DEFAULT*/
} apMCI_eClockMode;

/*
 * Description:
 * This defines the command response types.
 * The SD can support commands
 * with no response, short (1 unsigned long) or long (4 unsigned long) responses.  The
 * response expected must be passed when the command is invoked.
 */
typedef enum apMCI_xCmdResponse
{
    apMCI_CMDRESP_NONE   =0x00,        /*Command has no response*/
    apMCI_CMDRESP_SHORT  =0x01,        /*Command has short response*/
    apMCI_CMDRESP_LONG   =0x03        /*Command has long response*/
} apMCI_eCmdResponse;

/*
 * Description:
 * This enumerated type defines whether commands are allowed to time out.
 */
typedef enum apMCI_xCmdTimer
{
    apMCI_CMD_TIMEOUT    =FALSE,      /*Command timeout permitted*/
    apMCI_CMD_NOTIMEOUT  =TRUE        /*Command terminated only by interrupt*/
} apMCI_eCmdTimer;

/*
 * Description:
 * Standard commands supported by the Multimedia Card
 */
typedef enum apMCI_xCommand
{
  MCI_CMD0_GO_IDLE_STATE = 0,
  MCI_CMD1_SEND_OP_COND,
  MCI_CMD2_ALL_SEND_CID,
  MCI_CMD3_SET_RELATIVE_ADDR,
  MCI_CMD4_SET_DSR,
  MCI_CMD5,
  MCI_CMD6_SET_BUS_WIDTH,
  MCI_CMD7_SELECT_CARD,
  MCI_CMD8,
  MCI_CMD9_SEND_CSD,
  MCI_CMD10_SEND_CID,
  MCI_CMD11_READ_DAT_UNTIL_STOP,
  MCI_CMD12_STOP_TRANSMISSION,
  MCI_CMD13_SEND_STATUS,
  MCI_CMD14,
  MCI_CMD15_GO_INACTIVE_STATE,
  MCI_CMD16_SET_BLOCKLEN,
  MCI_CMD17_READ_SINGLE_BLOCK,
  MCI_CMD18_READ_MULTIPLE_BLOCK,
  MCI_CMD19,
  MCI_CMD20_WRITE_DAT_UNTIL_STOP,
  MCI_CMD21,
  MCI_CMD22,
  MCI_CMD23,
  MCI_CMD24_WRITE_BLOCK,
  MCI_CMD25_WRITE_MULTIPLE_BLOCK,
  MCI_CMD26,
  MCI_CMD27_PROGRAM_CSD,
  MCI_CMD28_SET_WRITE_PROT,
  MCI_CMD29_CLR_WRITE_PROT,
  MCI_CMD30_SEND_WRITE_PROT,
  MCI_CMD31,
  MCI_CMD32_TAG_SECTOR_START,
  MCI_CMD33_TAG_SECTOR_END,
  MCI_CMD34_UNTAG_SECTOR,            
  MCI_CMD35_TAG_ERASE_GROUP_START,
  MCI_CMD36_TAG_ERASE_GROUP_END,
  MCI_CMD37_UNTAG_ERASE_GROUP,
  MCI_CMD38_ERASE,
  MCI_CMD39_FAST_IO,
  MCI_CMD40_GO_IRQ_STATE,
  MCI_CMD41_SEND_OP_COND_SD,
  MCI_CMD42_LOCK_UNLOCK,
  MCI_CMD55_APP_CMD=55,
  MCI_CMD56_GEN_CMD
} apMCI_eCommand;
#define apMCI_MAX_COMMAND_NO 63

/*
 * Description:
 * This enumerated type defines the command status and matches the bit
 * pattern for the status register.  The detailed values can be checked
 * or the apMCI_CMDSTAT_PASS and apMCI_CMDSTAT_FAIL values can be used. 
 * There is one special cases - CMDSTAT_NOPOWER is returned if power-up
 * has not occurred
 */
typedef enum apMCI_xCmdStatus
{
    apMCI_CMDSTAT_NOPOWER   =-1,        /*SD not yet powered up*/
    apMCI_CMDSTAT_NONE      =0x00000,    /*No command status details*/
    apMCI_CMDSTAT_FAILCRC   =0x00001,    /*Command failed CRC check*/
    apMCI_CMDSTAT_TIMEOUT   =0x00004,    /*Command timed out*/
    apMCI_CMDSTAT_FAIL      =apMCI_CMDSTAT_FAILCRC | apMCI_CMDSTAT_TIMEOUT, /*Generic command failure*/
    apMCI_CMDSTAT_RESPOK    =0x00040,    /*Command response received*/
    apMCI_CMDSTAT_SENT      =0x00080,    /*Command completed - no response expected*/
    apMCI_CMDSTAT_PASS      =apMCI_CMDSTAT_RESPOK | apMCI_CMDSTAT_SENT,    /*Generic command success*/
    apMCI_CMDSTAT_INPROGRESS=0x00800,    /*Command still in progress*/
    apMCI_CMDSTAT_ERASE_UNSUPPORTED = 0x20000000, /*erase command not supported*/
    apMCI_CMDSTAT_ERASEFAIL =0x40000000  /*failure in Erase sequence*/
} apMCI_eCmdStatus;


/*
 * Description:
 * This enumerated type defines the data transfer status and matches the bit
 * pattern for the status register.
 */
typedef enum apMCI_xDataStatus
{
    apMCI_DATASTAT_NONE    =0x00000,    /*No data transfer*/
    apMCI_DATASTAT_FAILCRC =0x00002,    /*CRC failure in block check*/
    apMCI_DATASTAT_TIMEOUT =0x00008,    /*Timeout in data transfer*/
    apMCI_DATASTAT_UNDERRUN=0x00010,    /*Data underrun in Tx*/
    apMCI_DATASTAT_OVERRUN =0x00020,    /*Data overrun in Rx*/
    apMCI_DATASTAT_COMPLETE=0x00100,    /*Data transfer successful*/
    apMCI_DATASTAT_CMDFAIL =apMCI_CMDSTAT_FAIL, /*Failure in command to set up data*/
    apMCI_DATASTAT_BLOCKFAIL=0x40000000, /*data length does not divide into
                                          card blocks*/
    apMCI_DATASTAT_STATEFAIL=0x20000000,/*card has not entered expected state*/
    apMCI_DATASTAT_CARDFAIL=0x10000000, /*card returns an error*/
    apMCI_DATASTAT_ELAPSED=0x08000000,  /*Data transfer exceeds allowed time*/
    apMCI_DATASTAT_PAUSED=0x02000000,   /*Data transfer waiting for confirmation*/
    apMCI_DATASTAT_DATAFAIL =apMCI_DATASTAT_FAILCRC |
                             apMCI_DATASTAT_TIMEOUT |
                             apMCI_DATASTAT_UNDERRUN |
                             apMCI_DATASTAT_OVERRUN |
                             apMCI_DATASTAT_BLOCKFAIL |
                             apMCI_DATASTAT_STATEFAIL |
                             apMCI_DATASTAT_CARDFAIL  /*any data error*/
} apMCI_eDataStatus;

/*
 * Description:
 * These are the two return types for long/short responses.  It is up
 * to the user to interpret a response in the light of the command sent
 */
typedef union apMCI_xResponse
{
    unsigned long LongResponse[4];            /*long (4 word) format*/
    unsigned long ShortResponse;              /*short (1 word) format*/
} apMCI_sResponse;

/*
 * Description:
 * This enumerated type defines the power states.
 */
typedef enum MCI_xPowerState
{
    MCI_POWER_OFF =0x00,
    MCI_POWER_UP  =0x02,
    MCI_POWER_ON  =0x03
} MCI_ePowerState;


/*
 * Description:
 * On-card states
 */
typedef enum MCI_xCardState
{
    MCI_CARD_IDLE=0,
    MCI_CARD_READY,
    MCI_CARD_IDENT,
    MCI_CARD_STBY,
    MCI_CARD_TRAN,
    MCI_CARD_DATA,
    MCI_CARD_RCV,
    MCI_CARD_PRG,
    MCI_CARD_DIS,
    MCI_CARD_IGNORE         /*dummy entry*/
} MCI_eCardState;

/*
 * Description:
 * Bit offsets and masks for Command register
 */
#define bsMCI_CMD_INDEX        ( (unsigned long) 0)
#define bwMCI_CMD_INDEX        ( (unsigned long) 6)
#define bsMCI_CMD_RESPONSE     ( (unsigned long) 6)
#define bwMCI_CMD_RESPONSE     ( (unsigned long) 2)
#define bsMCI_CMD_INTERRUPT    ( (unsigned long) 8)
#define bwMCI_CMD_INTERRUPT    ( (unsigned long) 1)
#define bsMCI_CMD_PENDING      ( (unsigned long) 9)
#define bwMCI_CMD_PENDING      ( (unsigned long) 1)
#define bsMCI_CMD_ENABLE       ( (unsigned long) 10)
#define bwMCI_CMD_ENABLE       ( (unsigned long) 1)

/*
 * Description:
 * Bit masks for Status register
 */
#define MCI_STATUS_CMDCRCFAIL       ( (unsigned long) 0x000001)
#define MCI_STATUS_DATACRCFAIL      ( (unsigned long) 0x000002)
#define MCI_STATUS_CMDTIMEOUT       ( (unsigned long) 0x000004)
#define MCI_STATUS_DATATIMEOUT      ( (unsigned long) 0x000008)
#define MCI_STATUS_TXUNDERRUN       ( (unsigned long) 0x000010)
#define MCI_STATUS_RXOVERRUN        ( (unsigned long) 0x000020)
#define MCI_STATUS_CMDRESPEND       ( (unsigned long) 0x000040)
#define MCI_STATUS_CMDSENT          ( (unsigned long) 0x000080)
#define MCI_STATUS_DATAEND          ( (unsigned long) 0x000100)
#define MCI_STATUS_STARTBITERR      ( (unsigned long) 0x000200)
#define MCI_STATUS_DATABLOCKEND     ( (unsigned long) 0x000400)
#define MCI_STATUS_CMDACTIVE        ( (unsigned long) 0x000800)
#define MCI_STATUS_TXACTIVE         ( (unsigned long) 0x001000)
#define MCI_STATUS_RXACTIVE         ( (unsigned long) 0x002000)
#define MCI_STATUS_TXFIFOHALFEMPTY  ( (unsigned long) 0x004000)
#define MCI_STATUS_RXFIFOHALFFULL   ( (unsigned long) 0x008000)
#define MCI_STATUS_TXFIFOFULL       ( (unsigned long) 0x010000)
#define MCI_STATUS_RXFIFOFULL       ( (unsigned long) 0x020000)
#define MCI_STATUS_TXFIFOEMPTY      ( (unsigned long) 0x040000)
#define MCI_STATUS_RXFIFOEMPTY      ( (unsigned long) 0x080000)
#define MCI_STATUS_TXDATAAVLBL      ( (unsigned long) 0x100000)
#define MCI_STATUS_RXDATAAVLBL      ( (unsigned long) 0x200000)
/*this mask is all the static (clearable) bits*/
#define MCI_STATUS_STATIC_MASK      ( (unsigned long) 0x0007FF)
/*this mask is all bits which will generate a command interrupt*/
#define MCI_STATUS_CMD_INT_MASK    ( MCI_STATUS_CMDCRCFAIL | MCI_STATUS_CMDTIMEOUT | \
                                      MCI_STATUS_CMDSENT    | MCI_STATUS_CMDRESPEND| \
									 MCI_STATUS_CMDACTIVE )
/*this mask is all bits which will generate a data error*/
#define MCI_STATUS_DATA_ERR_MASK   ( MCI_STATUS_DATATIMEOUT | MCI_STATUS_RXOVERRUN   | \
                                      MCI_STATUS_STARTBITERR | MCI_STATUS_DATACRCFAIL | \
                                      MCI_STATUS_TXUNDERRUN)
/*this mask is all bits which will generate a fifo data interrupt*/
#define MCI_STATUS_DATA_FIFO_MASK  ( MCI_STATUS_TXFIFOEMPTY | MCI_STATUS_TXFIFOHALFEMPTY | \
                                      MCI_STATUS_RXFIFOFULL  | MCI_STATUS_RXFIFOHALFFULL  | \
                                      MCI_STATUS_RXDATAAVLBL)
/*this mask is all bits which will generate a data interrupt*/
#define MCI_STATUS_DATA_INT_MASK   ( MCI_STATUS_DATA_ERR_MASK   | MCI_STATUS_DATAEND     | \
                                      MCI_STATUS_DATABLOCKEND    | MCI_STATUS_TXFIFOEMPTY | \
                                      MCI_STATUS_TXFIFOHALFEMPTY | MCI_STATUS_RXFIFOFULL  | \
                                      MCI_STATUS_RXFIFOHALFFULL  | MCI_STATUS_RXDATAAVLBL )
/*this mask is all bits which are data related*/
#define MCI_STATUS_DATA_MASK       ( MCI_STATUS_DATA_INT_MASK | MCI_STATUS_TXACTIVE   | \
                                      MCI_STATUS_RXACTIVE     | MCI_STATUS_TXFIFOFULL | \
                                      MCI_STATUS_RXFIFOEMPTY )
/*this mask is all bits which will generate a read interrupt*/
#define MCI_STATUS_READ_INT_MASK   (  MCI_STATUS_DATA_ERR_MASK   | MCI_STATUS_DATAEND     | \
                                      MCI_STATUS_DATABLOCKEND    | MCI_STATUS_RXFIFOFULL  | \
                                      MCI_STATUS_RXFIFOHALFFULL  | MCI_STATUS_RXDATAAVLBL  )	 
/*this mask is all bits which will generate a write interrupt*/
#define MCI_STATUS_WRITE_INT_MASK   (  MCI_STATUS_DATA_ERR_MASK   | MCI_STATUS_DATAEND     | \
                                      MCI_STATUS_DATABLOCKEND     | MCI_STATUS_TXFIFOEMPTY  | \
									  MCI_STATUS_TXFIFOHALFEMPTY  | MCI_STATUS_TXFIFOFULL)
		
#define MCI_STATUS_DISABLE_INT_MASK	0
/*
 * Description:
 * Data direction modes (transmit or receive)
 */
typedef enum apMCI_xDataDirection
{
    apMCI_DATA_TRANSMIT =0x00,        /*Data sent from controller to card*/
    apMCI_DATA_RECEIVE  =0x01        /*Data sent from card to controller*/
} apMCI_eDataDirection;

/*
 * Description:
 * Data transfer modes (blocking or streaming)
 */
typedef enum apMCI_xDataBlocking
{
    apMCI_DATA_BLOCKING  =0x00,         /*Data sent with CRC checking*/